TDD Logical Units With Time Offset For Latency Reduction

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Solution Overview

Problem

Current Time Division Duplex (TDD) systems, such as DECT, face challenges in achieving low latency and high throughput, particularly in applications requiring ultra-reliable low latency communications and critical machine-type communications, as they are limited by latency constraints that exceed the requirements of many use cases.

Innovation Solution

The proposed solution involves activating multiple logical units within a communication unit to operate on the same frequency channel, with each logical unit allocated at least one time slot for each direction in a time slot structure, and coordinating their operation by introducing a relative time offset between the time slot structures to control communication delay and improve throughput and latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If traditional TDD systems use single logical unit with fixed time slot allocation, then system complexity is low and ease of operation is maintained, but latency cannot be reduced below inherent TDD constraints

Engineering Contradiction:
ImprovelatencyVSAvoidsystem complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent divides a single logical unit into multiple logical units (first logical unit and second logical unit), each with its own time slot structure. This segmentation allows parallel communication paths, reducing latency by enabling simultaneous transmissions in different time slots while maintaining manageable complexity through structured coordination.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a time offset dimension between the time slot structures of different logical units. By operating logical units with offset time slots rather than identical synchronized slots, the system creates an additional temporal dimension for resource allocation, enabling lower latency communications while avoiding complete synchronization complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Speed

If multiple logical units are activated to reduce latency, then communication delay is reduced, but coordination complexity between logical units increases

Engineering Contradiction:
Improvecommunication speedVSAvoidcoordination complexity
Core Design Contradiction:
SpeedVSEase of operation

Solution Approach 1:

The patent employs periodic time slot structures for each logical unit, with regular patterns of transmission and reception slots. This periodicity creates predictable, repeating communication cycles that simplify coordination compared to arbitrary scheduling, as the offset between logical units follows consistent temporal patterns that can be pre-configured and maintained.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent changes the time slot allocation parameters of logical units by introducing a relative time offset between them. This parameter modification allows the system to achieve faster communication speeds by optimizing slot positions, while the structured nature of the parameter changes maintains coordination simplicity through systematic rather than ad-hoc adjustments.

Inventive Principle:
Principle #35Parameter changes

3Loss of time

If time slot structures are offset to control communication delay, then latency is reduced, but synchronization requirements become more stringent

Engineering Contradiction:
Improvecommunication delayVSAvoidsynchronization reliability
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The patent establishes time offsets between logical units in advance, before actual communication occurs. This preliminary configuration of offset values allows the system to pre-calculate and pre-position time slots for optimal latency performance, while maintaining synchronization reliability through predetermined rather than dynamic timing adjustments.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3649815B1Improving the performance of a wireless time division duplex, TDD, system
Publication Date: 2021.12.22 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
  • EP3649815B1 patent drawingFigure 1
  • EP3649815B1 patent drawingFigure 2
  • EP3649815B1 patent drawingFigure 3

AI summary

There is provided a method of operating a first communication unit in a wireless TDD system, in which communication in two directions between the first communication unit and a second communication unit is separated by allocation of different time slots. The method comprises activating (S1), for the first communication unit, at least two logical units for operation with communication circuitry for enabling communication on the same frequency channel with communication circuitry and corresponding logical units in the second communication unit, each logical unit being allocated at least one time slot for each of the two directions in a time slot structure, wherein the time slot structure is clocked in time by a reference clock. The method also comprises coordinating (S2) the operation of the logical units of the first communication unit by introducing a relative time offset between the time slot structures of the logical units for controlling communication delay and enabling the offset to be maintained by using the same reference clock for the logical units.