TDDB Cell Profiling for Integrated Circuit FIT Reliability

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Solution Overview

Problem

The decreasing pitch and increasing gate count in semiconductor devices constrain reliability margins, with failures related to inter-metal dielectric time-dependent dielectric breakdown (TDDB) becoming significant due to reduced dimensions.

Innovation Solution

A method for constructing a time-dependent dielectric breakdown (TDDB) cell profile for each cell within a cell library, documenting valid voltage states and stress voltages across inter-conductor dielectrics, enabling accurate failure-in-time (FIT) rate derivation and strategic addressing of high-FIT cells to ensure reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If pitch is decreased and gate count is increased to advance technology, then device functionality and integration are improved, but reliability margins are constrained and TDDB failures become more significant

Engineering Contradiction:

Improvedevice functionality and integrationVSAvoidreliability margins and TDDB resistance

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by constructing TDDB cell profiles and documenting valid voltage states and stress voltages across inter-conductor dielectrics during the design phase. This allows potential reliability issues to be identified and addressed before manufacturing, enabling strategic mitigation of high-FIT cells while maintaining advanced device integration

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent segments the reliability analysis by creating individual TDDB cell profiles for each cell type in the cell library. Each profile documents specific voltage states and stress characteristics, allowing targeted identification and mitigation of high-FIT cells without compromising overall device functionality

Inventive Principle:

Principle #1Segmentation

2Quantity of substance

If dimensions are reduced to increase integration, then device density is improved, but TDDB failures become increasingly significant

Engineering Contradiction:

Improvedevice density and integrationVSAvoidTDDB resistance

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent applies local quality by documenting specific stress voltages and valid voltage states for each inter-conductor dielectric within individual cells. This localized analysis enables identification of specific high-FIT cells with reduced dimensions, allowing targeted mitigation strategies that preserve overall device density while addressing local reliability concerns

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20260050727A1Methods to derive failure-in-time rates of inter-conductor dielectric time-dependent dielectric breakdown for integrated circuits

Publication Date: 2026.02.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

The present disclosure provides a method which includes the following steps: obtaining an operation waveform of an integrated circuit which includes a plurality of cells; performing state mapping to each cell within the integrated circuit based on the obtained operation waveform; calculating state duties of one or more operational voltage states of each cell within the integrated circuit; calculating effective physical information of each inter-conductor dielectric within each cell using the state duties of the one or more operational voltage states of the respective cell; and calculating a failure-in-time rate of the integrated circuit from the effective physical information of each inter-conductor dielectric within each cell.