TDDB Test Circuit Array for Parallel Stress and Leakage Screening

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Solution Overview

Problem

The integration of semiconductor devices with thinner dielectric layers increases the time required for time-dependent dielectric breakdown (TDDB) testing, and performing the test on each device on a semiconductor substrate further prolongs the testing time.

Innovation Solution

A measurement circuit and method that applies high-level stress voltage to multiple test unit circuits in an array during global stress operations, followed by low-level stress voltage and current measurement to identify and flag leaky circuits, using a resistor in series with each device to protect it from high stress and improve accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If TDDB test is performed on each device on the semiconductor substrate, then measurement precision is improved, but loss of time increases

Engineering Contradiction:
ImproveTDDB measurement precisionVSAvoidtesting time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent segments the semiconductor substrate into multiple test unit circuits arranged in an array format, allowing parallel testing of multiple devices simultaneously. Each test unit circuit contains a device under test with its own dedicated test circuit, enabling concurrent TDDB measurements across many devices rather than sequential testing of individual devices.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent merges multiple test unit circuits into a single integrated array structure that shares common control and measurement resources. Multiple devices are combined into one test system where stress voltage can be applied simultaneously to all devices in the array, and leakage currents are measured in parallel through shared read circuits.

Inventive Principle:
Principle #5Merging (Combining)

2Productivity

If dielectric layer thickness is decreased, then device integration is improved, but loss of time increases

Engineering Contradiction:
Improvedevice integrationVSAvoidTDDB testing time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The test system is segmented into multiple independent test unit circuits that can operate in parallel, compensating for the increased test time required by thinner dielectric layers through simultaneous testing of multiple devices with the same thin dielectric.

Inventive Principle:
Principle #1Segmentation

3Productivity

If high-level stress voltage is applied to all circuits, then productivity is improved, but reliability decreases due to leakage current

Engineering Contradiction:
Improvetest throughputVSAvoidmeasurement accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements a two-stage testing approach where a preliminary low-level stress voltage is applied first to identify and flag leaky circuits before conducting the main high-level stress voltage test. This preliminary screening action prevents inaccurate measurements by excluding faulty circuits from the subsequent high-stress phase.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system continuously monitors leakage current during stress operations and uses this feedback to identify circuits that have broken down. When a circuit is flagged as leaky, the system adjusts by excluding it from further high-stress testing, using the measurement feedback to maintain overall test reliability.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20250383392A1Time-dependent dielectric breakdown (TDDB) test unit circuit, measurement circuit, and method thereof
Publication Date: 2025.12.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250383392A1 patent drawing
  • US20250383392A1 patent drawing
  • US20250383392A1 patent drawing

AI summary

A measurement circuit is provided. The measurement circuit includes an array including a plurality of test unit circuits arranged in rows and columns, a plurality of first test lines, a plurality of address lines and a control circuit connected to the plurality of address lines. Each test unit circuit includes a device under test, a resistor coupled in series with the device under test between an input terminal and an intermediate node, a first switch coupled between the intermediate node and a node of a reference voltage, and a second switch coupled between the intermediate node and an output terminal. Each first test line is connected to the first switches of the test unit circuits in a corresponding column of the array. Each address line is connected to the second switches of the test unit circuits in a corresponding row of the array.