TDM Audio Stream Buffering for Stable Multi-Clock Transfer
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Solution Overview
Problem
Existing multichannel audio systems face challenges in transporting signals from multiple audio sources over a serial port while maintaining accurate clock signals, particularly when the serial interface acts as a slave and requires efficient handling of different clock frequencies without complex hardware or software solutions that may compromise audio quality.
Innovation Solution
A method utilizing a buffering mechanism and state machine implemented as a software component, which manages direct memory access (DMA) to align buffer positions and adjust clock frequencies, allowing for concurrent data transfer and minimizing jitter and underrun/overrun issues, even with a low-end CPU, by deriving clock signals from a single PLL source.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple PLLs are used to generate different clock signals for multiple audio sources, then clock signal accuracy is improved, but device complexity and cost increase
Solution Approach 1:
The patent merges multiple clock signal generation functions into a single PLL by using programmable frequency dividers. Instead of using separate PLLs for each audio source, one PLL generates a master clock that is then divided into multiple different clock frequencies using programmable dividers, reducing hardware complexity while maintaining clock accuracy
Solution Approach 2:
The single PLL is designed to serve multiple functions by generating a master clock signal that can be divided into various frequencies to support multiple audio sources with different sampling rates. The programmable dividers allow the same PLL to adapt to different clock requirements dynamically
2Adaptability or versatility
If sample rate conversion is implemented to handle different clock frequencies, then compatibility with multiple audio sources is improved, but processing complexity and computational load increase
Solution Approach 1:
The system performs preliminary clock frequency division before data processing. By dividing the master clock frequency into appropriate frequencies for each audio source in advance, the system avoids the need for complex sample rate conversion during audio data processing, reducing computational load
Solution Approach 2:
Programmable frequency dividers act as intermediaries between the single PLL and multiple audio sources. These dividers convert the master clock into the required frequencies for each source, mediating the clock synchronization without requiring complex sample rate conversion algorithms
3Reliability
If buffer sizes are increased to reduce underrun/overrun issues, then audio flow stability is improved, but audio latency increases
Solution Approach 1:
The system dynamically adjusts buffer management based on the synchronized clock frequencies. By using accurately divided clock signals, the system can optimize buffer sizes and transfer timing dynamically, maintaining stability with smaller buffers compared to systems with clock frequency drift that would require larger buffers for compensation
4Device complexity
If a single PLL is used to generate all clock signals, then device complexity is reduced, but maintaining accurate clock synchronization across different audio sources becomes difficult
Solution Approach 1:
The clock generation system is segmented into two functional parts: a single PLL for generating the master clock, and multiple programmable frequency dividers for creating source-specific clock frequencies. This segmentation allows one PLL to serve multiple purposes while maintaining accurate synchronization through programmable division ratios
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient and accurate transfer of multichannel audio signals with acceptable latency, avoiding the need for multiple PLLs and complex sample rate conversion, thus ensuring long-term audio flow stability and compatibility with low-end processing units.
Implementation Method 1
obtain the input clock frequency and the TDM output clock frequency from clock frequency division of a master clock frequency (e.g. PLL)
Data Source
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AI summary
A method of producing a TDM serial audio stream comprises: - receiving plural input audio signal streams (CDS, TS, BTS, E) from an audio source (AS) clocked at an input clock frequency (AUDIOclk) and producing therefrom a time domain multiplex, TDM, serial output stream clocked at a TDM output clock frequency (TDMclk), - obtaining the input clock frequency (AUDIOclk) and the TDM output clock frequency (TDMclk) by clock frequency division (DIV, TDMdiv, AUDIOdiv; 20, 22, 24) of a master clock frequency (PLL), - providing a set of memory buffers (100; BUFFO, BUFF1, BUFF2, BUFF3), and - writing audio signal samples from the input audio signal streams into the set of memory buffers (100; BUFF0, BUFF1, BUFF2, BUFF3) with writing clocked at the input clock frequency (AUDIOclk), and - producing the TDM serial output stream from audio signal samples buffered in the memory buffers (100; BUFF0, BUFF1, BUFF2, BUFF3) by reading the buffered audio signal samples with reading clocked at the TDM output clock frequency (TDMclk).