Time Division Multiplexed Bus for Modular Systems

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Solution Overview

Problem

Modular computing systems face challenges in providing efficient and robust communication among blades, passthrough modules, and chassis management controllers, particularly with hot-swapping causing data integrity issues and requiring low latency without increasing pin count.

Innovation Solution

A time division multiplexed (TDM) communication bus that allocates specific time slots for data packets with error check data, ensuring data integrity by validating all packets within a frame before utilization, and reducing the number of signal lines through a multi-drop control bus with synchronization and clock signals combined.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dedicated low level signal pins are used for communication among blades, PTMs and CMCs, then communication reliability is improved, but pin count and device complexity increase

Engineering Contradiction:
Improvecommunication reliabilityVSAvoidpin count
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple communication functions (data transmission, error checking, synchronization, and device identification) into a single TDM communication bus. Instead of using separate dedicated signal pins for each function, the system multiplexes all communications over one shared bus, thereby reducing pin count while maintaining communication reliability through protocol-level error detection and validation mechanisms.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The TDM communication bus serves multiple functions simultaneously: it transmits data packets between devices, performs error checking through checksum validation, provides synchronization via time slots, and identifies devices through addressed communication. This multi-functional approach eliminates the need for separate dedicated pins for each function, reducing overall device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If time division multiplexing is implemented with error checking for all data packets, then data integrity is improved, but communication latency increases

Engineering Contradiction:
Improvedata integrityVSAvoidcommunication latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs error checking on all data packets within a frame before any device utilizes the data. This preliminary validation ensures data integrity by catching errors early, while the structured frame-based approach allows devices to process multiple packets efficiently in batches, reducing overall communication latency compared to individual packet validation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The TDM system uses periodic time slots to transmit data packets from different devices in a structured frame sequence. Each device transmits during its allocated time slot, and error checking is performed periodically on complete frames. This periodic structure ensures data integrity through systematic validation while maintaining low latency by preventing collisions and ensuring predictable transmission timing.

Inventive Principle:
Principle #19Periodic action

3Adaptability or versatility

If hot-swapping of blades is allowed, then system adaptability is improved, but data integrity problems occur

Engineering Contradiction:
Improvehot-swapping capabilityVSAvoiddata integrity
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The TDM communication protocol includes feedback mechanisms through error check data in each packet and frame-level validation. When blades are hot-swapped, the system continuously monitors communication integrity through checksum validation. If data integrity is compromised during hot-swapping, the error detection feedback allows the system to identify and correct issues, ensuring reliable operation despite dynamic configuration changes.

Inventive Principle:
Principle #23Feedback

4Productivity

If multiple data packets are transmitted simultaneously on a communication bus, then communication speed is improved, but data integrity and error detection become more difficult

Engineering Contradiction:
Improvecommunication speedVSAvoiderror detection capability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The communication bus transmits data in segmented frames, with each frame containing multiple data packets from different devices. Each packet includes error check data, and the entire frame undergoes validation. This segmentation allows simultaneous transmission of multiple packets (increasing communication speed) while maintaining error detection capability through structured validation at both packet and frame levels.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The TDM system dynamically allocates time slots to different devices based on their communication needs. Multiple devices can transmit data packets simultaneously in their respective time slots within a frame, increasing overall communication throughput. The dynamic time-division structure ensures that packets from multiple sources are organized systematically, allowing error detection mechanisms to validate each packet's integrity despite the concurrent transmissions.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS7848232B2Time division multiplexed communication bus and related methods
Publication Date: 2010.12.07 DELL PROD LP
  • US7848232B2 patent drawing
  • US7848232B2 patent drawing
  • US7848232B2 patent drawing

AI summary

A time division multiplexed communication bus is disclosed that provides a low latency, low pin count solution for communications among information handling systems. The time division multiplexed serial bus is advantageous in providing communications among modular computing systems, passthrough modules and chassis management controllers, as part of a modular computing system chassis.