Time-division-multiplexed Display Driver with Variable Switch Timing
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Solution Overview
Problem
In high-definition liquid crystal display panels using polysilicon TFTs, the time available for writing gray scale voltages into sub-pixels is insufficient in conventional time-division multiplexed driving methods, leading to inadequate display quality due to unequal writing times for red, green, and blue video lines.
Innovation Solution
The display device employs a video line drive circuit that outputs gray scale voltages time-sequentially to blocks of video lines, with switch groups ensuring that the last switch is turned on for a longer duration, allowing sufficient time for writing gray scale voltages into sub-pixels by adjusting the timing and duration of video line selection pulses, thereby ensuring Tm > Tq and T - Ts > T/m.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If time-division multiplexed driving is used to reduce the number of output pins, then device complexity is reduced, but the writing time for gray scale voltages becomes insufficient
Solution Approach 1:
The patent applies dynamics by making the switch turning-on timings variable rather than uniform. Specifically, the switching timings are adjusted dynamically so that switches corresponding to video lines with longer required writing times turn on earlier, while switches for video lines with shorter required writing times turn on later. This dynamic adjustment of switching timings ensures sufficient writing time for all video lines while maintaining the time-division multiplexed driving structure that reduces output pin count.
Solution Approach 2:
The patent changes the timing parameters of switch operations to resolve the contradiction. By varying the turn-on timings of different switches within the time-division multiplexed sequence, the system ensures that each video line receives adequate writing time. The parameter being changed is the temporal position at which each switch activates, allowing optimization of writing time distribution across multiple video lines without increasing the number of output pins.
2Device complexity
If video lines are divided into blocks for time-sequential signaling, then the number of output terminals is reduced, but the writing time distribution becomes unequal among video lines
Solution Approach 1:
The patent applies asymmetry by intentionally creating unequal switch turning-on timings to compensate for the unequal writing time distribution. Instead of using uniform time intervals for all switches, the system employs asymmetric timing where earlier switches in the sequence turn on at different intervals than later switches. This asymmetric timing distribution ensures that video lines receiving signals later in the sequence (which would otherwise have shorter writing time) are compensated by having their switches turn on earlier relative to their position in the sequence, thereby achieving uniform effective writing time across all video lines.
3Manufacturing precision
If sub-pixel pitch is reduced for higher definition, then display quality is improved, but routing of interconnection wiring becomes difficult
Solution Approach 1:
The patent applies segmentation by dividing the video lines into multiple blocks and using time-division multiplexed switching to route signals to these blocks. This segmentation approach allows the system to manage the increased number of video lines required for higher definition displays by grouping them into manageable blocks that can be controlled by fewer output terminals. The time-division multiplexing further segments the signal transmission in time, allowing one output terminal to serve multiple video lines sequentially, thereby reducing routing complexity despite the increased number of video lines needed for higher definition.
Data Source
AI summary
A display device includes sub-pixels, video lines, a drive circuit and switch groups. The video lines are divided into plural blocks each composed of m video lines, m being an integer of 2 or more. The drive circuit outputs m gray scale voltages time-sequentially. Each of the switch groups corresponding to one of the blocks is composed of first to mth switches, receives the m gray scale voltages from the drive circuit, and then supplies them to the m video lines in a time-division multiplexed fashion. The mth switch is turned on last during a writing time for writing the m gray scale voltages into the sub-pixels, and Tq<Tm, where Tm and Tq are times during which the mth switch and a qth switch of the first to (m−1)th switches are turned on, respectively, and q is an integer of from 1 to (m−1).