Time-division multiplexing circuitry for FPGA simulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing complexity of integrated circuits with multiple processing cores makes it difficult to simulate designs using field programmable gate arrays (FPGAs), leading to significant price and performance disadvantages due to the need for multiple FPGA representations and slow off-chip communications.
Innovation Solution
Implementing time-division multiplexing of processing circuitry, where a single instance of processing circuitry is clocked at a higher rate to simulate multiple instances, using multiplexing and demultiplexing circuitry to select and process signals, reducing the need for multiple FPGA representations and enhancing processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple instances of processing circuitry are formed on an integrated circuit to increase data processing throughput, then processing capacity is improved, but device complexity and gate count increase making simulation difficult
Solution Approach 1:
The patent applies time-division multiplexing where a single processing core periodically executes instructions for multiple virtual processors in sequential time slots. Each virtual processor receives dedicated time slices, creating the illusion of parallel processing while using a single physical core, thereby maintaining high throughput without increasing gate count
Solution Approach 2:
The single processing core is designed to perform multiple functions by dynamically switching between different virtual processor contexts. The same physical hardware resources (ALU, registers, cache) are universally utilized across different virtual processors, eliminating the need for duplicate hardware instances and reducing overall device complexity
2Reliability
If a single integrated circuit with multiple processing cores is represented by multiple FPGA integrated circuits, then simulation capability is achieved, but cost and communication overhead increase
Solution Approach 1:
The patent merges multiple virtual processor functions into a single FPGA-based processing system. By implementing time-division multiplexing within one FPGA device, the system consolidates what would otherwise require multiple separate FPGA circuits, reducing inter-chip communication needs and lowering overall system complexity while maintaining full simulation capability
3Reliability
If multiple FPGA integrated circuits are used to represent a single SMP integrated circuit, then adequate modeling is achieved, but off-chip communication speed decreases performance
Solution Approach 1:
The patent combines multiple virtual processor models into a single FPGA device using time-division multiplexing, eliminating the need for off-chip communication between multiple FPGA circuits. All processing operations occur within the same chip, ensuring that communication between virtual processors happens through fast on-chip interconnects rather than slow off-chip links, thereby maintaining both model accuracy and high communication speed
Data Source
AI summary
An integrated circuit including multiple instances of identical processing circuitry may be modelled within a field programmable gate array integrated circuit by second processing circuitry connected via a multiplexer to first processing circuitry and operating at a multiple of the clock frequency of the first processing circuitry. Demultiplexing circuitry is used to reform the multiple outputs of the respective separate instances to be fed back to the first processing circuitry.