Memory Controller TDM Access for Nonvolatile Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional systems with multiple processes accessing a nonvolatile memory device often experience latency issues due to conflicts between competing processes, leading to unpredictable performance, and increasing the number of NVM devices to address this problem results in higher costs and system size.
Innovation Solution
Implementing a time division multiplexing (TDM) arrangement where each processing core is assigned specific slots to access designated banks of a nonvolatile memory device, ensuring that different cores access different banks in a predetermined order to prevent conflicts and optimize access times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple processes compete for a same NVM device, then arbitration processes are required to prioritize accesses, but this leads to variable latency and unpredictable performance
Solution Approach 1:
The NVM device is segmented into multiple banks, and each master process is assigned to specific banks. This segmentation eliminates the need for arbitration by allowing each master to access its dedicated banks without interference from other masters, thereby providing predictable access latency while maintaining reliability.
2Loss of time
If the number of NVM devices is increased to dedicate some to particular processes, then latency for some processes is ensured, but this greatly increases the cost and size of the system
Solution Approach 1:
Multiple NVM banks are merged into a single NVM device, creating an internal structure that provides dedicated access paths for different masters. This approach ensures low latency for each process while avoiding the need to increase the number of separate NVM devices, thereby controlling system size and cost.
Solution Approach 2:
The patent introduces a new dimension of organization within the NVM device by creating multiple banks with dedicated access paths. This internal dimensional structure allows multiple processes to have guaranteed latency performance without requiring multiple separate physical NVM devices.
3Productivity
If the number of NVM devices is increased to dedicate some to particular processes, then process-specific performance is improved, but this increases the cost of the system
Solution Approach 1:
A single NVM device is designed to serve multiple masters simultaneously through its multi-bank structure. Each master receives dedicated performance guarantees for its assigned banks, making the single NVM device universal in its ability to serve multiple processes with high productivity without increasing system cost.
Data Source
AI summary
A device can include a plurality of processing sources; a multiplexer (MUX) configured to assign read requests from the processing sources to predetermined time division multiplexer (TDM) command slots. A memory controller can generate nonvolatile memory (NVM) command and address data from read requests received from the MUX during the TDM command slots assigned to the read requests on a unidirectional command-address bus. The address data can include at least a bank address. The device can also receive read data on a unidirectional parallel data bus in synchronism with rising and falling edges of a received data clock. The read data can be received in TDM read slots having a predetermined order. A demultiplexer can provide the read data of each TDM read slot to one of the processing sources based on the TDM read slot position in the predetermined order. Related methods and systems are also disclosed.