Time Division Multiplexed Single-Port Memory for Dual-Port Bandwidth
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Solution Overview
Problem
Dual-port SRAMs face challenges in area efficiency and the occurrence of read-disturb-write and write-disturb-write situations due to the need for additional transistors and wires for an additional port, which can lead to inefficiencies and errors in memory operations.
Innovation Solution
Implementing a time division multiplexing (TDM) circuit that allows a single-port memory to operate in a shared manner, using an external clock signal to generate internal clock pulses, enabling concurrent read and write operations without the need for additional ports, thereby preventing disturb situations and improving area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dual-port SRAM is implemented with additional ports for each bit cell, then bandwidth is increased to about 2× of single-port SRAMs, but area efficiency deteriorates due to additional transistors and wires occupying additional area
Solution Approach 1:
The patent applies time division multiplexing to alternate between first and second port operations in periodic time slots. The memory device switches between servicing the first port during first time slots and the second port during second time slots, enabling dual-port functionality with single-port hardware by using periodic time-based separation of operations
Solution Approach 2:
The patent dynamically switches the operational mode of the memory device between different port configurations. Control logic dynamically selects which port is active during each time slot, allowing the same physical port to serve multiple functional roles at different times, thereby achieving dual-port bandwidth without dual-port hardware
2Productivity
If dual-port SRAM is implemented with additional ports for each bit cell, then concurrent read and write operations are enabled, but read-disturb-write and write-disturb-write situations occur due to simultaneous operations on the same row
Solution Approach 1:
The patent uses periodic time division multiplexing to separate read and write operations into different time slots. By alternating between first port operations and second port operations in periodic intervals, simultaneous conflicting operations on the same row are prevented, eliminating read-disturb-write and write-disturb-write errors while maintaining concurrent operation capability
Solution Approach 2:
The patent maintains continuous memory operations by seamlessly switching between ports in alternating time slots. The control logic ensures that while one port is performing read operations, the other port can perform write operations, and vice versa, maintaining continuous productive activity without conflicts through proper timing coordination
3Area of stationary object
If single-port SRAM cells with shared port are used for dual-port implementation, then area efficiency is improved, but bandwidth is reduced compared to true dual-port SRAM
Solution Approach 1:
The patent employs time division multiplexing with periodic switching between first and second port time slots. This allows the single-port memory to achieve effective dual-port bandwidth by rapidly alternating service between ports, maintaining area efficiency while recovering productivity through time-based parallelism
Solution Approach 2:
The patent changes the temporal parameters of memory operations by introducing periodic time slot allocation. By adjusting the timing and duration of first and second port operations, the system optimizes the effective bandwidth achieved through time multiplexing while maintaining single-port hardware configuration
Data Source
AI summary
In some embodiments, a time division multiplexing (TDM) circuit is configured to receive an external clock signal and generate an internal clock signal that has at least one pulse during a clock cycle of the external clock signal. An address selector is configured to select a current address before a first time within one of the at least one pulse, and select a next address starting from the first time to generate a selected address. An address storage element is configured to receive the selected address from the address selector and provide a passed through or stored address. The provided address is the current address substantially throughout the one of the at least one pulse. A single-port (SP) memory is configured to access at least one SP memory cell at the address provided by the address storage element in response to the internal clock signal.