Variable Resistance Memory Electrode Layout Using TDMIT Sidewall Protection
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Solution Overview
Problem
Conventional semiconductor device fabrication processes face inefficiencies due to the redeposition of TDMIT material during patterning, leading to shunt failures and increased turnaround times, particularly when forming electrode layers for variable resistance memory cells.
Innovation Solution
Incorporating a TDMIT material in the middle and upper electrode layers, which redeposits on the sidewalls of the variable resistance layer to form a sidewall protection layer, reducing the need for multiple ion beam etching processes and enhancing process efficiency by allowing the TDMIT material to exhibit both conductive and insulating properties based on thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple ion beam etch processes are used to remove redeposited materials, then manufacturing precision is improved, but productivity deteriorates due to increased process time
Solution Approach 1:
The patent extracts and removes the harmful redeposited material layer formed during ion beam etching by using a separate removal process. This separates the etching function from the cleanup function, allowing each to be optimized independently and eliminating the need for multiple iterative etching cycles.
Solution Approach 2:
The patent introduces an intermediary removal process between the ion beam etching steps. This intermediary process specifically targets and removes the redeposited materials without requiring additional etching cycles, acting as a mediator that cleans up the contaminants created during the main etching process.
2Manufacturing precision
If multiple ion beam etch processes are used to remove redeposited materials, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent extracts the removal function from the etching process sequence. Instead of using multiple etching processes where each removes different layers, the patent uses one etching process followed by a dedicated removal process that handles all redeposited materials, simplifying the overall process architecture.
Solution Approach 2:
The patent merges the removal of different types of deposited materials into a single removal process. Rather than requiring separate etching processes for different layers, the patent combines multiple removal operations into one unified process step, reducing process complexity.
3Ease of manufacture
If conventional etching processes are used, then manufacturing simplicity is maintained, but shunt failures increase
Solution Approach 1:
The patent applies a preliminary action by forming a protective layer or modifying the etching environment before the main etching process. This preliminary modification prevents shunt failures from occurring during the etching process, allowing conventional simple etching processes to proceed without causing reliability issues.
Solution Approach 2:
The patent converts the potentially harmful effect of ion beam etching (which causes redeposition and shunt failures) into a beneficial process by controlling the etching conditions or adding protective measures that transform the harmful redeposition into a controlled feature, eliminating shunt failures while maintaining process simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces shunt failures and turnaround times by utilizing the redeposition of TDMIT material to form a protective sidewall layer, improving the overall efficiency and ease of the fabrication process while maintaining the necessary conductivity and insulation properties.
Implementation Method 1
a thickness dependent metal-insulator transition (TDMIT) material that exhibits an electrical resistance depending on a thickness of the TDMIT material
Implementation Method 2
which redeposits on the sidewalls to form a protective layer
Data Source
AI summary
An semiconductor device may include a first conductive line; a second conductive line disposed to be spaced apart from the first conductive line; a variable resistance layer disposed between the first conductive line and the second conductive line; and an electrode layer which is disposed at least one of a first location between the first conductive lines and the variable resistance layer, or a second location between the variable resistance layer and the second conductive lines and includes a thickness dependent metal-insulator transition (TDMIT) material that exhibits an electrical resistance depending on a thickness of the TDMIT material.


