TDMR Read Channel Timing and Equalization
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Solution Overview
Problem
In magnetic recording systems, as track pitch decreases, one-dimensional codes and detectors struggle with Inter Track Interference (ITI), leading to performance issues, which Two Dimensional Magnetic Recording (TDMR) aims to address by utilizing multiple read heads and advanced signal processing techniques.
Innovation Solution
A system employing two read channels with analog to digital converters and a single digital timing loop, along with a two-dimensional equalizer, asymmetry correction blocks, variable gain amplifiers, and finite impulse response filters, to process signals from overlapping tracks, effectively handling ITI and improving data reading accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If track pitch is decreased to increase recording density, then more tracks can be stored on the medium, but Inter Track Interference (ITI) increases and degrades reading performance
Solution Approach 1:
The patent transitions from traditional one-dimensional reading (single read head per track) to two-dimensional reading by employing multiple read heads that read adjacent tracks simultaneously. This dimensional change allows the system to capture signals from multiple tracks and use signal processing to separate and reconstruct the desired track data, effectively mitigating ITI while maintaining high recording density
Solution Approach 2:
The patent introduces signal processing techniques as an intermediary between the physical read heads and the data output. The read channels process signals from multiple heads, applying algorithms to separate overlapping track signals and eliminate ITI effects before presenting clean data to the user, thus resolving the interference problem without changing the physical track layout
2Reliability
If multiple read channels are employed to read adjacent tracks, then ITI can be mitigated, but hardware complexity and cost increase
Solution Approach 1:
The patent merges the functionality of multiple read channels by using a single shared digital timing loop to control interpolation of timing of sampling for all ADCs. This shared control mechanism reduces the number of independent timing circuits needed, thereby lowering hardware complexity while still enabling simultaneous reading from multiple tracks
Solution Approach 2:
The patent implements universal signal processing components that handle signals from multiple read heads. The read channels are designed with common functional blocks that can process signals from any combination of heads, reducing overall system complexity through component reuse and standardized processing paths
3Measurement precision
If separate timing loops are used for each read channel, then timing can be precisely controlled, but synchronization complexity and latency increase
Solution Approach 1:
The patent combines multiple separate timing loops into a single shared digital timing loop that controls all ADCs in the system. This unified timing mechanism maintains precise timing control for all read channels while eliminating the synchronization complexity and latency that would arise from coordinating multiple independent timing loops
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies data path synchronization, reduces hardware costs, and enhances read signal alignment, leading to improved data reading performance and reduced latency in TDMR systems.
Implementation Method 1
When retrieving data, magnetic field variations can be converted into an analog electrical signal
Data Source
AI summary
This application includes systems and techniques relating to storage devices, such as a device including: a first read channel to process a first input signal obtained from a storage medium using a first read head; a second read channel to process a second input signal obtained from the storage medium using a second read head, which is offset from the first read head in each of two dimensions; a single digital timing loop configured to control interpolation of timing of sampling for first and second analog to digital converters in the first and second read channels; and a two dimensional equalizer coupled with output lines of the first and second read channels; the device being configured to account for a fractional timing difference between the first input signal and the second input signal, the fractional timing difference being a fractional amount of a single clock cycle of the device.