Backside Power Delivery Structure Using TDVs to Cut IR Drop
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) shrink in size, the complexity of processing and manufacturing increases, particularly in packing contact features on one side of a substrate, leading to challenges in power delivery networks due to high parasitic resistance and current-resistance (IR) drops.
Innovation Solution
The formation of a semiconductor structure with a backside power delivery network (PDN) that includes a through dielectric via (TDV) disposed vertically between metal lines, reducing parasitic resistance and IR drops during power delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If contact features are packed on one side of the substrate, then functional density increases, but parasitic resistance and IR drops increase
Solution Approach 1:
The patent introduces a third dimension by routing power delivery network features through the thickness of the substrate. Through-substrate vias and backside power rails extend the power delivery path from a single-sided planar configuration to a three-dimensional architecture, allowing power to be delivered from both the front and back sides of the chip, thereby reducing parasitic resistance and IR drops while maintaining high functional density.
2Quantity of substance
If routing features are moved to the backside of the substrate, then packing density improves, but device complexity increases
Solution Approach 1:
The patent segments the power delivery network into distinct functional regions: frontside power rails, backside power rails, and through-substrate via regions. This segmentation allows each region to be optimized independently for its specific function while maintaining overall system integration. The modular approach simplifies the manufacturing process by enabling sequential formation of each segment through standardized fabrication steps.
3Reliability
If through dielectric via is used, then parasitic resistance decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary patterning and alignment steps where via holes are formed with precise positioning relative to the power rails before metal deposition. The fabrication process includes pre-defined via locations that are established early in the manufacturing sequence, allowing subsequent metal filling and planarization steps to proceed with relaxed tolerance requirements. This preliminary structuring ensures accurate via placement while maintaining manufacturability.
Data Source
AI summary
A semiconductor structure and a method of forming the same are provided. In an embodiment, a method includes receiving a workpiece comprising a first transistor and a second transistor formed over a first side of a substrate, forming a first multi-layer interconnect (MLI) structure over the first side of the substrate, wherein the first MLI structure comprising a first plurality of metal lines and a first plurality of vias, after the forming of the first MLI structure, forming a source/drain contact directly under a source/drain feature of the first transistor, and forming a second MLI structure under the source/drain contact and under a second side of the substrate, the second side being opposite the first side, wherein the MLI structure comprises a second plurality of metal lines and a second via, a thickness of the second via is greater than a thickness of one of the first plurality of vias.