TEC Receiver Sampling Without CDR Using Delay-Line Transition Detection
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Solution Overview
Problem
Conventional Transition Enforcing Coding (TEC) receivers require Clock and Data Recovery (CDR) circuits, leading to increased chip area, power consumption, and production costs, especially when handling wide ranges of data rates.
Innovation Solution
A TEC receiver design that eliminates the need for CDR by using a delay line circuit, transition detection circuit, and skew calibration circuit to determine sampling timing without relying on clock and data recovery, allowing for correct sampling of vector signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a CDR circuit is implemented in the TEC receiver to adjust sampling timing, then correct data sampling is achieved, but chip area increases and power consumption increases
Solution Approach 1:
The patent extracts and removes the CDR circuit from the TEC receiver architecture, replacing it with a simplified timing adjustment mechanism that uses delay elements and transition detection logic. This extraction eliminates the complex feedback loops and phase detectors inherent in traditional CDR circuits, thereby reducing chip area while maintaining sampling accuracy through alternative means.
Solution Approach 2:
The patent creates a simplified copy of the CDR functionality using discrete delay elements and transition detection circuits rather than implementing a full CDR system. This copy achieves the essential timing adjustment function without replicating the complex structure of a traditional CDR circuit, reducing area overhead while preserving the core capability of synchronized data sampling.
2Reliability
If a CDR circuit is implemented in the TEC receiver to adjust sampling timing, then correct data sampling is achieved, but power consumption increases
Solution Approach 1:
The patent removes the power-hungry CDR circuitry including phase detectors, voltage-controlled oscillators, and feedback loops, replacing them with low-power delay elements and transition detection logic. This extraction eliminates continuous power consumption associated with maintaining phase lock while achieving timing synchronization through event-driven sampling based on detected signal transitions.
Solution Approach 2:
The patent enables the receiver to self-adjust sampling timing by detecting transitions in the incoming data signal itself, rather than requiring an external CDR circuit to continuously monitor and adjust phase. The transition detection circuit uses the signal's own edges to trigger sampling, creating a self-synchronizing mechanism that consumes minimal power compared to active CDR systems.
3Adaptability or versatility
If a wide-range CDR circuit is implemented to cover various data rates, then adaptability is improved, but production cost increases
Solution Approach 1:
The patent implements dynamic delay adjustment through selectable delay paths that can be configured for different data rates without requiring a complex wide-range CDR circuit. The system adapts to various data rates by dynamically selecting appropriate delay element combinations, providing versatility through reconfigurable timing rather than through a continuously adjustable CDR mechanism, thereby simplifying manufacturing.
Solution Approach 2:
The patent segments the delay adjustment function into discrete, selectable delay stages that can be independently configured for different data rate requirements. This segmentation allows the use of standard, easily manufactured delay elements in specific combinations rather than requiring a continuous, wide-range adjustable CDR circuit, reducing production complexity and cost while maintaining adaptability across data rates.
4Measurement precision
If a CDR circuit is used in the TEC receiver, then sampling timing is optimized, but lock-in time is required which increases delay
Solution Approach 1:
The patent applies preliminary delay adjustment through fixed delay elements configured to provide appropriate timing margins before data sampling occurs. Rather than requiring a lock-in period for the CDR circuit to converge on the correct phase, the system pre-configures delay paths to establish optimal sampling timing from the outset, eliminating the time loss associated with CDR acquisition and lock-in procedures.
Data Source
AI summary
A transition enforcing coding (TEC) receiver includes a delay line circuit, a transition detection circuit, a data sampling circuit, and a skew calibration circuit. The delay line circuit employs a calibrated delay setting to delay a plurality of vector signals to generate a plurality of delayed vector signals under a normal mode, respectively. The transition detection circuit detects a transition of at least one specific delayed vector signal among the delayed vector signals. The data sampling circuit samples the vector signals according to a sampling timing, wherein the sampling timing is determined based on an output of the transition detection circuit. The skew calibration circuit sets the calibrated delay setting under a calibration mode, wherein transition skew between different delayed vector signals is reduced by the calibrated delay setting under the normal mode.