TEC Receiver Sampling via Transition Detection Without CDR
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Solution Overview
Problem
Conventional Transition Enforcing Coding (TEC) receivers require Clock and Data Recovery (CDR) circuits, leading to increased chip area, power consumption, and production costs, especially when handling wide ranges of data rates.
Innovation Solution
A TEC receiver design that eliminates the need for CDR by using a combination of delay line and transition detection circuits to determine sampling timing, allowing correct sampling of vector signals without CDR, thereby reducing chip area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a CDR circuit is implemented in the TEC receiver to adjust sampling timing, then correct data sampling is achieved, but chip area increases
Solution Approach 1:
The patent extracts and removes the CDR circuit from the TEC receiver architecture, replacing it with a transition detection mechanism that uses the inherent transition properties of TEC-encoded signals to generate sampling clocks, thereby eliminating the need for dedicated CDR hardware and reducing chip area
Solution Approach 2:
The system uses the signal's own transition characteristics to generate the sampling clock internally, making the receiver self-sufficient without requiring external CDR circuits, thus achieving correct sampling while minimizing additional hardware
2Reliability
If a CDR circuit is implemented in the TEC receiver to adjust sampling timing, then correct data sampling is achieved, but power consumption increases
Solution Approach 1:
The CDR circuit is removed from the architecture, eliminating its power consumption entirely and replacing it with a more energy-efficient transition detection approach that leverages the signal's inherent properties
Solution Approach 2:
The receiver generates its own sampling timing from the signal transitions without requiring power-hungry CDR circuitry, achieving accurate sampling through self-service timing generation
3Adaptability or versatility
If a wide-range CDR circuit is implemented to handle various data rates, then adaptability is improved, but production cost increases
Solution Approach 1:
The transition detection circuit serves multiple functions across different data rates without requiring adjustment or reconfiguration, providing universal adaptability to various TEC data rates while maintaining a simple, cost-effective implementation
Solution Approach 2:
The patent employs a simple, fixed delay line structure that does not require expensive wide-range CDR circuitry, achieving cost-effective manufacture while maintaining adaptability through the inherent properties of the TEC encoding scheme
4Reliability
If a CDR circuit is implemented in the TEC receiver, then sampling timing adjustment is achieved, but lock-in time is increased
Solution Approach 1:
The transition detection circuit is prepared to immediately detect signal transitions and generate sampling clocks from the first received transitions, eliminating the lock-in time required by CDR circuits to acquire and lock onto the data rate and phase
Data Source
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AI summary
A transition enforcing coding (TEC) receiver (400, 1000, 1500, 1600, 1700) includes a first delay line circuit (402, 1502), a transition detection circuit (404, 1504), and a data sampling circuit (406, 1006, 1508). The first delay line circuit (402, 1502) delays a plurality of vector signals (s[0]-s[m-1]) to generate a plurality of delayed vector signals (s[0]_D-s[m-1]_D), respectively. The transition detection circuit (404, 1504) detects a transition of at least one specific delayed vector signal among the delayed vector signals (s[0]_D-s[m-1]_D). The data sampling circuit (406, 1006, 1508) samples the vector signals (s[0]-s[m-1]) according to a sampling timing determined based on an output of the transition detection circuit (404, 1504).