Automated TEG Layout Equalizing Wiring Resistance

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Solution Overview

Problem

The challenge lies in accurately evaluating variations in semiconductor elements due to differences in manufacturing apparatuses and process conditions, which affect the electrical characteristics of semiconductor devices, and existing manual layout methods for Test Element Groups (TEGs) are inefficient and prone to design failures.

Innovation Solution

A control system that automatically generates a TEG layout using a program to equalize wiring resistances and employs a learning model to arrange TEG blocks on a substrate based on in-plane distribution data, ensuring precise evaluation of semiconductor elements and minimizing the impact of manufacturing apparatus variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If manual layout methods are used for TEG, then design flexibility is maintained, but efficiency is low and design failures occur

Engineering Contradiction:

Improvelayout generation efficiencyVSAvoiddesign accuracy

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The system enables automatic layout generation where the computer program autonomously creates TEG layouts without manual intervention, eliminating human error while maintaining design requirements through automated constraint satisfaction

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

Manual mechanical layout drawing is replaced by an automated computer-based system that uses algorithms to generate layouts, substituting human manual operations with automated computational processes to improve both efficiency and reliability

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Measurement precision

If wiring resistances are not equalized, then layout generation is simpler, but evaluation accuracy of semiconductor elements is compromised

Engineering Contradiction:

Improvesemiconductor element evaluation accuracyVSAvoidlayout generation complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The system automatically equalizes wiring resistances in the TEG layout by adjusting wire routes and dimensions, ensuring that all measurement paths have equivalent electrical characteristics, which eliminates resistance-induced measurement errors and improves evaluation accuracy

Inventive Principle:

Principle #12Equipotentiality

Solution Approach 2:

The system dynamically adjusts wiring parameters such as wire width, length, and routing during automatic layout generation to achieve equal resistance values across different measurement paths, transforming the layout design process into a parameter-optimization problem

Inventive Principle:

Principle #35Parameter changes

3Measurement precision

If TEG blocks are not optimally placed on substrate, then placement process is faster, but in-plane variation evaluation is inaccurate

Engineering Contradiction:

Improvein-plane variation measurement accuracyVSAvoidlayout generation time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The system performs preliminary analysis of substrate in-plane variations and pre-determines optimal TEG block placement positions before final layout generation, ensuring that measurement points are strategically located to capture variation patterns while automating the time-consuming placement process

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20220382937A1Layout method for automatically generating circuit layout and control system for controlling layout arrangement of circuit generated over substrate

Publication Date: 2022.12.01 SEMICON ENERGY LAB CO LTD

AI summary

A novel circuit layout method is provided. In a circuit including a first terminal, a second terminal, a third terminal, a fourth terminal, a first wiring, and a second wiring, the layout method includes a step of generating a layout of connecting the first terminal and the third terminal using the first wiring; a step of generating a layout of connecting the second terminal and the fourth terminal using the second wiring; a step of calculating a first wiring resistance of the first wiring; a step of calculating a second wiring resistance of the second wiring; and a step of automatically generating the layouts of the first wiring and the second wiring in the circuit so that the first wiring resistance can be equal to the second wiring resistance.