TEG Pattern Visibility in Multi-Layer Semiconductor Wiring
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Solution Overview
Problem
In semiconductor devices with multi-layered wiring, the Test Element Group (TEG) patterns are often obscured by dummy patterns, making them invisible and preventing external testing unless the layers over the TEG patterns are removed.
Innovation Solution
The TEG pattern is designed to eliminate overlap with all wiring and dummy patterns in a planar view, allowing it to remain visible and usable for testing without the need to remove the layers above it by forming it in a manner that prevents overlap with these structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If multiple wiring layers with dummy patterns are formed over the TEG pattern, then the film thickness uniformity is improved, but the TEG pattern becomes invisible and cannot be tested externally
Solution Approach 1:
The patent resolves the contradiction by transitioning from a two-dimensional planar arrangement to a three-dimensional spatial arrangement. The TEG pattern is positioned at a different vertical level (depth) than the wiring layers, allowing it to be accessible for testing while the wiring layers maintain their protective and uniforming function overhead. This vertical separation in the z-dimension enables both film thickness uniformity and TEG pattern testability to coexist.
2Productivity
If dummy patterns are automatically arrayed by design support device, then the design efficiency is improved, but the TEG pattern is covered and cannot be accessed for testing
Solution Approach 1:
The patent applies preliminary action by pre-defining a pattern array prohibition area during the design stage where dummy patterns and wiring layers are prohibited from being formed. This advance planning ensures that the TEG pattern remains accessible for testing while still allowing automated design support devices to efficiently generate dummy patterns in permitted areas, thus maintaining design efficiency without compromising TEG accessibility.
3Difficulty of detecting and measuring
If layers over the TEG pattern are removed to enable testing, then the TEG pattern becomes visible, but additional processing steps are required
Solution Approach 1:
The patent extracts the TEG pattern from beneath the wiring layers by positioning it in a separate vertical zone that is not covered by the wiring structures. This extraction eliminates the need to remove or etch away protective layers to access the TEG pattern, as it remains naturally accessible from the front surface while the wiring layers maintain their integrity overhead, thereby reducing processing complexity.
Data Source
AI summary
Unless layers over a TEG pattern are removed, a test using the TEG pattern is conducted. Multiple wiring layers are formed over a first TEG pattern. A wiring and multiple dummy patterns are formed in each of the wiring layers. An electrode pad is formed in an uppermost wiring layer. In a planar view, the first TEG pattern eliminates overlap with all of the wirings and the dummy patterns.