Semiconductor TEG Well Structure for Accurate Gate Resistance Measurement
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Solution Overview
Problem
Current semiconductor wafer testing methods face challenges in accurately measuring gate vertical resistance due to parasitic resistance and capacitance components, which affect the accuracy of electric property evaluation and increase processing time.
Innovation Solution
The implementation of test element groups (TEGs) with a specific configuration, including floating p-wells and deep n-wells, reduces pad-well parasitic capacitance while maintaining noise shielding, allowing for precise measurement of gate vertical resistance through high-frequency impedance analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional test element groups are used for measuring gate vertical resistance, then the measurement can be performed, but parasitic resistance and capacitance components reduce measurement accuracy
Solution Approach 1:
The test element group is segmented into multiple functional components: the first test transistor for measurement, the second test transistor for parasitic compensation, and multiple wells (p-well, n-well, deep n-well) for electrical isolation. This segmentation allows separate functions to be performed by distinct structural elements, enabling accurate gate vertical resistance measurement by compensating for parasitic effects.
Solution Approach 2:
The second test transistor serves as an intermediary element that measures parasitic resistance and capacitance components. By using this intermediary measurement, the actual gate vertical resistance can be calculated by subtracting the parasitic components from the total measured resistance, thereby improving measurement accuracy.
2Measurement precision
If deeper wells are added to reduce parasitic capacitance, then measurement accuracy improves, but device complexity increases
Solution Approach 1:
Different regions of the test element group are assigned different structural qualities: the deep n-well is implemented only in specific areas where parasitic capacitance reduction is most critical, while other regions use standard well structures. This local differentiation optimizes parasitic reduction where needed without unnecessarily increasing complexity throughout the entire device.
Solution Approach 2:
The well structures are nested hierarchically: the p-well is surrounded by the n-well, which is in turn surrounded by the deep n-well in certain regions. This nested configuration achieves effective electrical isolation and parasitic capacitance reduction through layered protection, maximizing the shielding effect while using a compact structure.
3Measurement precision
If multiple test transistors are used to compensate for parasitic effects, then measurement accuracy improves, but processing time increases
Solution Approach 1:
The second test transistor is configured to measure parasitic resistance and capacitance components in advance of the actual gate vertical resistance measurement. By performing this preliminary parasitic characterization, the compensation values are obtained beforehand, allowing the main measurement to be completed more quickly with accurate correction already prepared.
Solution Approach 2:
The measurement functions of both test transistors are merged into a single integrated test element group structure that shares common wells and substrate. This combined configuration allows both parasitic measurement and gate vertical resistance measurement to be performed in close proximity, reducing overall testing time while maintaining compensation accuracy.
Data Source
AI summary
According to one or more embodiments of the disclosure, an apparatus comprising a pad above a semiconductor substrate, an n-well in the semiconductor substrate, and a floating p-well in the semiconductor substrate is provided. The floating p-well is below the pad and surrounded by the n-well in the semiconductor substrate.