Temperature-Dependent Select Gate Voltage for Non-Volatile Memory Erase
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Solution Overview
Problem
Non-volatile memory devices face challenges in efficiently erasing data at low temperatures due to reduced gate-induced drain leakage (GIDL) current, which slows down the erase process.
Innovation Solution
A control circuit generates temperature-dependent select gate voltages and adjusts erase pulse durations and magnitudes to ensure sufficient GIDL current, combining these techniques to improve erase speed at lower temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional erase operations are used at low temperatures, then power consumption is reduced, but erase speed decreases due to reduced GIDL current
Solution Approach 1:
The patent applies dynamics by making the select gate voltage temperature-dependent rather than fixed. The control circuit dynamically adjusts the magnitude of the select gate voltage based on detected temperature conditions, transitioning from a static voltage approach to a dynamic adaptive one that responds to environmental changes and maintains optimal erase performance across temperature ranges
Solution Approach 2:
The patent changes the parameter of select gate voltage magnitude based on temperature conditions. At low temperatures, the control circuit increases the magnitude of the select gate voltage to compensate for reduced GIDL current, while at higher temperatures, it uses conventional voltage levels. This parameter adjustment directly addresses the temperature-dependent performance variation
2Speed
If higher select gate voltages are applied to compensate for low temperature effects, then erase speed is improved, but device complexity increases due to temperature sensing and adaptive control
Solution Approach 1:
The control circuit performs self-service by autonomously detecting temperature conditions and automatically adjusting the select gate voltage magnitude without external intervention. The system monitors its own operating conditions and self-regulates the voltage output, eliminating the need for complex external control mechanisms while maintaining optimal erase performance across temperature ranges
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances erase speed and efficiency by optimizing select gate voltages and erase pulse parameters based on temperature, ensuring effective data erasure even at low temperatures.
Implementation Method 1
A control circuit is configured to generate a select gate voltage having a magnitude that depends on a present temperature. The select gate voltage is applied to a control gate of a select transistor while an erase voltage is applied to a bit line or source line associated with the string. The select gate voltage, in combination with the erase voltage, generates a gate induced drain leakage (GIDL) current
Data Source
AI summary
Apparatuses and techniques are described for temperature dependent erase in non-volatile storage. In one aspect, select gate voltage magnitude depends on temperature. This temperature dependent select gate voltage may be applied to a control gate of a select transistor while applying an erase voltage to a bit line and/or source line coupled to the select transistor. This can help assure that there is sufficient GIDL current for efficient erase at lower temperatures. In one aspect, a control circuit increases the duration of the erase voltage that is applied to the source line and/or the bit line at lower temperatures. In one aspect, the magnitude of the first erase voltage in a sequence depends on the present temperature.