Temperature Compensation in Solid-State Memory

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Solution Overview

Problem

Solid-state memory devices, such as flash drives, face reduced endurance due to temperature variations, leading to increased program disturb failures and bit-error rates, which existing solutions like reduced step size and programming schemes fail to adequately address without compromising performance or increasing design complexity.

Innovation Solution

Implementing a temperature compensation system that uses a temperature sensor to adjust program verify and read levels, shifting these levels to maintain even programming state distributions and improve memory endurance by offsetting verify levels based on detected temperature and programming cycles.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If temperature compensation is not applied, then device complexity remains low, but bit-error rate increases and endurance deteriorates at high temperatures

Engineering Contradiction:
Improvememory enduranceVSAvoidtemperature compensation system
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system uses an on-chip temperature sensor to automatically detect temperature conditions and adjust program verify levels without external intervention. The controller self-regulates the compensation based on detected temperature, eliminating the need for complex external temperature control circuits while maintaining reliability.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent dynamically adjusts program verify levels based on detected temperature conditions. At different temperatures, different verify levels are applied during programming to compensate for temperature-induced threshold voltage shifts, thereby maintaining memory endurance without requiring fundamental system redesign.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If program verify levels are shifted to compensate for temperature, then bit-error rate reduces, but programming operation complexity increases

Engineering Contradiction:
Improvebit-error rateVSAvoidprogramming operation
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The system implements a feedback mechanism where the controller continuously monitors temperature via the on-chip sensor and adjusts program verify levels accordingly. This closed-loop approach automatically compensates for temperature effects during programming operations, reducing bit-error rates while keeping the programming interface simple for users.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The controller acts as an intermediary between the temperature sensor and the programming operation. It translates temperature conditions into appropriate verify level adjustments, shielding the user from complexity while ensuring accurate programming at varying temperatures.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Stability of the object's composition

If standard program verify levels are used without temperature adjustment, then device complexity remains low, but programming state distribution becomes uneven at high temperatures

Engineering Contradiction:
Improveprogramming state distributionVSAvoidverify level adjustment mechanism
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The system performs preliminary temperature detection and verify level adjustment before programming operations commence. By pre-compensating for temperature effects based on sensor readings, the system ensures even programming state distribution from the outset, preventing threshold voltage drift issues before they occur.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements dynamic adjustment of program verify levels based on real-time temperature conditions. Rather than using fixed verify levels, the system adaptively modifies them during programming operations to maintain consistent state distribution across varying temperatures, achieving stability through dynamic control.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9672934B2Temperature compensation management in solid-state memory
Publication Date: 2017.06.06 PALISADE TECH LLP
  • US9672934B2 patent drawing
  • US9672934B2 patent drawing
  • US9672934B2 patent drawing

AI summary

Systems and methods are disclosed for programming data in a non-volatile memory array are disclosed. A data storage device includes a non-volatile memory array including a plurality of non-volatile memory cells and a controller configured to receive a signal indicating a temperature of at least a portion of the data storage device. The controller determines a first offset program verify level associated with a first programming level based at least in part on the temperature and programs a first set of the memory cells of the non-volatile memory array using the first offset program verify level.