Temperature-Varying Write Circuit for Programmable Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory devices, such as DRAMs and EEPROMs, face challenges due to temperature sensitivity of storage elements, which affects their performance and reliability as device geometries shrink and power consumption requirements become more stringent, making them less desirable for modern applications.
Innovation Solution
The implementation of a memory device with a programmable impedance element memory array and a temperature varying write circuit that adjusts electrical conditions based on temperature changes, using programmable metallization cells (PMCs) and ion conductor layers to alter write characteristics, ensuring consistent write times across a range of temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory devices (DRAMs and EEPROMs) are used, then data storage function is achieved, but temperature sensitivity of storage elements deteriorates performance and reliability
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting write voltage and write pulse width based on detected temperature conditions. The write circuit modifies electrical parameters (voltage magnitude and pulse duration) to compensate for temperature-induced variations in memory element characteristics, thereby maintaining reliable operation across different temperatures
Solution Approach 2:
The patent implements feedback through a temperature detection mechanism that monitors thermal conditions and provides information to the write circuit. This feedback loop enables the system to automatically adjust write operations based on real-time temperature measurements, counteracting temperature sensitivity effects
2Quantity of substance
If device geometries are shrunk to increase integration, then device density is improved, but temperature sensitivity increases and performance deteriorates
Solution Approach 1:
The patent compensates for temperature sensitivity in scaled devices by dynamically changing write operation parameters. As devices are shrunk and become more temperature-sensitive, the system adjusts voltage and timing parameters in real-time based on temperature detection, enabling high-density devices to maintain performance despite increased temperature sensitivity
3Device complexity
If write operations are performed without temperature compensation, then device complexity is reduced, but write time varies unpredictably with temperature
Solution Approach 1:
The patent reduces write time variability by implementing parameter changes in the write operation. The system detects temperature and adjusts write voltage and pulse width accordingly, ensuring consistent write performance across temperature ranges. This approach accepts increased circuit complexity as a trade-off for eliminating unpredictable write time variations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach compensates for temperature-induced variations in memory elements, maintaining predictable device operation and reducing temperature sensitivity, thereby enhancing the reliability and efficiency of memory devices.
Implementation Method 1
A memory device may include a programmable impedance element memory array and a temperature varying write circuit
Implementation Method 2
A current source circuit may be connected to a bit line or group of bit lines within a memory array
Data Source
AI summary
An integrated circuit device can include a plurality of memory cells, each including at least one element programmable between different impedance states by application of a voltage or current; a plurality of bit line groups, each bit line group including multiple bit lines, each bit line being coupled to multiple memory cells; a plurality of current source circuits coupled to the bit line groups, each current source circuit configured to couple the bit lines of its respective group to at least a first bias node or a second bias node.