Template-Based User Defined Instructions in Out-of-Order Processors
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Solution Overview
Problem
In out-of-order processor systems with deeply pipelined architectures, the incorporation of user-defined instructions leads to increased latency and blocking of standard instruction set instructions due to the need for the main core to wait for information from the user execution block, resulting in inefficient processing.
Innovation Solution
A system where the main processing core decodes out-of-order instructions, including template-based user-defined instructions, with a user execution block executing these instructions, adhering to a specified pattern that includes a source, destination, and latency period, allowing for efficient execution and bypassing of results through completion buffers to avoid stalls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If user-defined instructions are incorporated into the main core processor flow with a user execution block, then user-defined instructions can be executed, but the main core has to wait for information from the user execution block which increases latency and blocks standard instruction set instructions
Solution Approach 1:
The processor is divided into a main core for standard instructions and a separate user execution block for user-defined instructions. The user execution block operates independently with its own decoder and execution block, segmented from the main core's pipeline stages. This segmentation allows user-defined instructions to be executed without blocking the main core's standard instruction flow, resolving the latency issue while maintaining versatility.
Solution Approach 2:
An intermediary interface is introduced between the main core and user execution block to coordinate instruction execution. The interface includes a dispatch unit that manages instruction routing and a completion mechanism that notifies the main core when user-defined instructions are finished. This intermediary coordination eliminates the need for the main core to wait for user execution block information, reducing latency while supporting user-defined instructions.
2Productivity
If user-defined instructions are decoded and executed in a separate user execution block, then the main core can continue processing, but the user execution block has to inform the main core about the nature and properties of the user defined instruction which increases latency
Solution Approach 1:
The user execution block is pre-configured with a decoder that automatically decodes user-defined instructions upon receipt from the main core. The execution block is pre-prepared with execution resources and a completion notification mechanism is pre-established. This preliminary setup eliminates the need for real-time communication about instruction nature and properties, allowing the main core to continue processing without latency interruptions while maintaining high productivity.
3Speed
If the main core is an out of order execution machine with a deeply pipelined architecture, then processing speed is improved, but the user execution block increases latency when coordinating with the main core
Solution Approach 1:
The user execution block is extracted as a separate, independent unit from the main deeply pipelined core. It has its own decoder (130) and execution block (132) that operate independently of the main core's pipeline stages (110-124). This extraction allows the main core to maintain its high-speed out-of-order execution without being slowed down by coordination latency with the user execution block, as the user block processes instructions autonomously and notifies completion without interrupting the core's pipeline.
Data Source
AI summary
A system implemented in hardware includes a main processing core decoding instructions for out of order execution. The instructions include template based user defined instructions. A user execution block executes the template based user defined instructions. An interface is positioned between the main processing core and the user execution block. A computer readable medium includes executable instructions to describe a processing core supporting execution of a proprietary instruction set and decoding of customized instructions that adhere to a specified pattern. The specified pattern includes a source, a destination and a latency period. A user execution block is connected to the processing core to execute the customized instructions.