Engineered Template Transfer of Metal Interconnect Layers
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Solution Overview
Problem
Conventional semiconductor manufacturing processes for forming metal interconnect layers are complex, costly, and potentially damaging to device substrates, while new approaches for flexible and stretchable electronics have lower throughputs and resolutions, limiting their adoption.
Innovation Solution
The method involves forming metal interconnect layers on engineering templates using established semiconductor techniques and transferring them to device substrates, using engineered templates that are resistant to processing conditions and can be reused, allowing for asynchronous operations and reducing substrate damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional semiconductor manufacturing processes are used to form metal interconnect layers on device substrates, then manufacturing precision and reliability are improved, but device complexity and potential damage to substrates increase
Solution Approach 1:
The manufacturing process is segmented into two independent stages: (1) forming metal interconnect layers on engineered templates using semiconductor techniques, and (2) transferring the formed interconnect layers to device substrates. This segmentation allows the complex formation process to be decoupled from the substrate, reducing overall process complexity while maintaining precision.
Solution Approach 2:
An engineered template is introduced as an intermediary carrier to hold the metal interconnect layers during formation. The template serves as a temporary support that withstands processing conditions and facilitates subsequent transfer to the device substrate, simplifying the overall manufacturing流程.
2Manufacturing precision
If conventional electroplating processes are used on device substrates, then manufacturing precision is improved, but substrate damage increases
Solution Approach 1:
The harmful electroplating process is extracted from the device substrate and performed instead on the engineered template. The template is specifically designed to withstand these harsh processing conditions, thereby protecting the device substrate from damage while maintaining precise interconnect formation.
Solution Approach 2:
The metal interconnect layers are formed in advance on the engineered template before the device substrate is introduced. This preliminary formation allows the substrate to be protected from damaging processing conditions while still achieving precise interconnect structures through subsequent transfer.
3Adaptability or versatility
If flexible and stretchable electronics approaches are used, then adaptability is improved, but productivity and manufacturing precision deteriorate
Solution Approach 1:
The engineered template serves multiple functions: it withstands harsh processing conditions, enables high-precision interconnect formation, and facilitates transfer to various device substrates including flexible and stretchable electronics. This multi-functionality allows conventional high-productivity semiconductor techniques to be applied while maintaining adaptability to different substrate types.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the complexity and cost of the process, minimizes substrate damage, and enables the use of well-established semiconductor techniques, while allowing for the integration of flexible and stretchable electronics with higher throughput and resolution.
Implementation Method 1
MILs are formed using semiconductor techniques, such as physical vapor deposition, electroplating/selective electroplating, etch-back, and the like
Implementation Method 2
The method also comprises selectively electroplating the transferable MIL into the template features over the seed layer
Data Source
AI summary
Described herein are methods and systems for forming metal interconnect layers (MILs) on engineered templates and transferring these MILs to device substrates. This “off-device” approach of forming MILs reduces the complexity and costs of the overall process, allows using semiconductor processes, and reduces the risk of damaging the device substrates. An engineered template is specially configured to release a MIL when the MIL is transferred to a device substrate. In some examples, the engineered template does not include barrier layers and/or adhesion layers. In some examples, the engineered template comprises a conductive portion to assist with selective electroplating. Furthermore, the same engineered template may be reused to form multiple MILs, having the same design. During the transfer, the engineered template and device substrate are stacked together and then separated while the MIL is transitioned from the engineered template to the device substrate.