Templatized Memory Pattern Generator for Fewer Test Vectors
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Solution Overview
Problem
Traditional memory testing methods are inefficient due to the exponential increase in test vectors with increasing pins and memory capacity, leading to high error rates and limited reusability.
Innovation Solution
A templatized memory pattern generator integrates a simple memory pattern generator (SMPG) into the test processor, calculating parallel test data based on algorithms and reducing the need for explicit pin state representations, using an SMPG resource mapping table to map data to device under test pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional test schemes are used to serially represent test vectors for all pins in each cycle, then complete coverage of all storage units can be achieved, but the number of test vectors increases exponentially with the number of pins and memory capacity
Solution Approach 1:
The patent segments the test vector representation by separating address generation from data generation. Instead of representing all pin states simultaneously, the system generates address vectors and data vectors independently through dedicated generators (address generator, data generator) that operate based on temporal relationships, thereby reducing the exponential growth of test vectors while maintaining complete coverage.
Solution Approach 2:
The patent introduces a temporal dimension to the test vector representation. Instead of representing all pin states in a single static vector, the system uses time-based generation where address and data are generated sequentially based on timing signals. This temporal dimension allows the system to reduce the number of simultaneous vectors needed while maintaining comprehensive test coverage through time-multiplexed operations.
2Reliability
If the number of test vectors increases exponentially with pins and memory capacity, then complete storage unit traversal is achieved, but test efficiency decreases and error rates increase
Solution Approach 1:
The patent implements self-service by enabling the address generator and data generator to automatically produce test vectors based on temporal relationships and predefined sequences. The generators operate autonomously using timing signals and internal state, eliminating the need for manual pattern construction and reducing human error. This automated self-service approach maintains comprehensive coverage while significantly improving test efficiency.
3Reliability
If patterns are used to statically represent test vectors, then test coverage can be defined, but reusability of the test scheme is limited
Solution Approach 1:
The patent transforms the static pattern representation into a dynamic test vector generation system. Instead of using fixed patterns that must be manually rewritten for different configurations, the system employs temporal generators that dynamically produce address and data vectors based on timing signals and current state. This dynamic approach maintains comprehensive coverage while significantly enhancing reusability across different memory configurations.
Solution Approach 2:
The patent achieves universality by designing the address generator and data generator to operate with different memory configurations through a single unified architecture. The generators can adapt to various pin counts and memory capacities by utilizing temporal relationships and state-based generation, eliminating the need for separate test patterns for each configuration. This multi-functional design maintains comprehensive coverage while enabling broad reusability.
Data Source
AI summary
The templatized memory pattern generator includes a test processor, a simple memory pattern generator, a channel timing & formatter, and a pin electronic. The simple memory pattern generator includes an X address generator, a Y address generator, a D data generator, a SMPG and channel mapping. An input terminal of the channel timing & formatter is connected to the SMPG and channel mapping; and parallel data calculated by the simple memory pattern generator based on an SMPG resource mapping table provided by an upper computer is mapped to pins of a device under test one by one. The present disclosure can effectively reduce a quantity of test vectors in an image file. Meanwhile, after modulation, the scheme can improve the reusability of a test program and reduce the development period of the test scheme.