Temporal Buffering for Asynchronous Integrity Comparison in SoCs
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Solution Overview
Problem
Existing systems-on-chip face challenges in synchronizing asynchronous hardware events due to timing differences between dissimilar processors, leading to complex and costly data/execution synchronization schemes, which are ineffective in detecting common mode faults.
Innovation Solution
A system-on-chip design incorporating application and integrity processing cores with different instruction set architectures, where the integrity monitor performs temporal buffering and compares outputs to detect valid or mis-compare, using a strike counter to manage fault detection and reset the system upon threshold exceedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If temporal buffering is implemented to handle timing differences between processors, then measurement precision is improved, but device complexity increases
Solution Approach 1:
A timestamp intermediary mechanism is introduced that attaches temporal markers to data packets at the source processor. These timestamps serve as mediators that allow the receiving processor to understand and compensate for timing differences without requiring complex real-time synchronization protocols between processors.
Solution Approach 2:
Timing information is captured and recorded in advance when data is generated, rather than attempting to synchronize processors in real-time. The timestamp is attached to the data packet before transmission, enabling post-hoc temporal alignment and comparison at the receiving end.
2Device complexity
If asynchronous operation is used to simplify design, then device complexity is reduced, but reliability deteriorates due to undetected common mode faults
Solution Approach 1:
The system implements a feedback mechanism where the receiving processor compares incoming data against previously stored data using temporal buffering. Discrepancies detected through this feedback loop trigger fault detection protocols, allowing the system to identify common mode faults even while operating asynchronously.
Solution Approach 2:
The system dynamically adjusts its fault detection sensitivity based on the strike counter state. When temporal misalignment is detected, the system can temporarily reduce sensitivity to avoid false positives, then resume normal fault detection once synchronization is restored, allowing flexible operation in varying conditions.
3Reliability
If strike counter mechanism is implemented to detect faults, then reliability is improved, but loss of time increases due to system resets
Solution Approach 1:
The strike counter mechanism uses a threshold-based approach where faults are detected after multiple occurrences rather than immediately. This partial action approach reduces false positives from transient errors, while the excessive action of requiring multiple strikes before triggering a reset ensures that only persistent faults cause system interruptions.
Data Source
AI summary
A system-on-chip may include application processing cores which execute safety critical applications and an integrity application. The system-on-chip may also include integrity processing cores which execute an integrity monitor. The integrity monitor may compare integrity application outputs and integrity monitor outputs to detect if the processing cores have experienced a common mode fault. The integrity processing cores may perform temporal monitoring to accommodate time-asynchronization's between the application processing cores and the integrity processing cores.