Temporal Memory Circuits Using Tunable Delays for Race Logic
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Solution Overview
Problem
Current computational architectures are limited by the stagnation of transistor design and performance, and the lack of practical implementations for race logic encoding schemes, which encodes multi-bit information in a single edge per wire, hindering efficient data storage and processing.
Innovation Solution
The development of temporal memory systems using tunable delay components that encode and store data in the time domain, allowing for efficient read and write operations without digital conversion, and enabling the use of race logic principles in computer architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If digital clocked schemes are used for data storage and processing, then computational operations can be performed reliably, but energy consumption increases and performance improvement stagnates
Solution Approach 1:
The patent changes the fundamental parameter of data encoding from digital voltage levels to temporal arrival times of wavefronts. By encoding multi-bit information in the timing domain rather than voltage domain, the system reduces energy consumption associated with digital transitions while maintaining computational capability through time-based operations
Solution Approach 2:
The patent replaces the traditional digital clocked computational system with a temporal encoding system using wavefronts and delay elements. This substitution eliminates the need for clocked digital transitions that consume energy, while achieving computational operations through time-based signal processing
2Use of energy by moving object
If race logic encoding is implemented to reduce energy consumption, then energy efficiency improves, but practical implementation feasibility decreases
Solution Approach 1:
The patent segments the temporal memory into multiple delay elements, each handling specific time delays. This segmentation allows the complex temporal encoding system to be built from simpler, modular delay components that are easier to manufacture and integrate into existing architectures
Solution Approach 2:
The patent introduces tunable delay elements as intermediary components between wavefront inputs and outputs. These delay elements act as mediators that convert temporal encoding into stored delay values, which can then be read out as temporal signals, bridging the gap between theoretical race logic and practical implementation
3Device complexity
If multiple bits are encoded on a single wire using arrival time encoding, then wiring complexity reduces, but measurement and detection difficulty increases
Solution Approach 1:
The patent replaces complex multi-wire parallel encoding with single-wire temporal encoding using wavefront arrival times. By substituting spatial multiplexing with temporal multiplexing, the system reduces wiring complexity while the timing measurement is facilitated through delay element comparisons rather than complex signal detection
Data Source
AI summary
Various design concepts, circuit implementations, and methods are provided for implementing temporal memory. For example, temporal memories may perform both read and write operations using time-encoded wavefronts. A temporal memory may include a group of tunable delay components that “store” time-encoding information. Using these delay components, the memory can perform a “read” operation by outputting wavefronts having the same or similar time-encoding as the stored wavefronts. Temporal memories may allow for more energy-cost-efficient operation and may serve as building blocks for more complex temporal computational circuits.