Temporal Virtualization Circuit for Multi-Thread Isolation
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Solution Overview
Problem
Current electronic design automation (EDA) tools face challenges in efficiently supporting temporal virtualization on target devices like FPGAs and ASICs, particularly in managing multiple threads and ensuring secure resource sharing without spatial replication, while maintaining trust and isolation between clients.
Innovation Solution
The method involves transforming a circuit to support multiple threads by adding components for state management, thread swapping, and generating interfaces that prevent data interference between threads, allowing for secure and efficient resource utilization through time-division multiplexing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single circuit is shared among multiple clients through spatial virtualization, then resource utilization is improved, but trust and isolation between clients deteriorate
Solution Approach 1:
The patent segments the shared circuit into multiple isolated execution contexts by introducing context identifiers and context-specific control logic. Each client's execution is segmented into distinct state spaces, preventing interference while maintaining shared hardware resources. The segmentation is achieved through context registers, state memory, and control signals that differentiate between multiple clients accessing the same circuit.
Solution Approach 2:
The patent introduces intermediary mechanisms including context management logic, state memory, and control registers that mediate between multiple clients and the shared circuit. These intermediaries enforce isolation by controlling which client can access which circuit state at any given time, thereby maintaining trust while enabling resource sharing.
2Reliability
If multiple spatially distinct circuits are implemented for different functions, then isolation between circuits is improved, but device area and complexity worsen
Solution Approach 1:
The patent merges multiple functionally distinct circuits into a single shared physical circuit by implementing temporal virtualization. The same hardware resources are reused across different functional contexts through time-division multiplexing, controlled by context identifiers and state management logic. This combining approach maintains functional isolation while dramatically reducing the required device area.
Solution Approach 2:
The patent transforms a single circuit into a universal resource that can serve multiple functional purposes through temporal virtualization. The circuit implements multiple functions sequentially by switching between different execution contexts, each with its own state space and control parameters, thereby eliminating the need for separate dedicated circuits for each function.
3Reliability
If circuit state is replicated for multiple threads, then thread isolation is improved, but device area and power consumption worsen
Solution Approach 1:
The patent implements periodic switching between different thread contexts rather than maintaining simultaneous replicated states. The circuit periodically transitions between serving different threads by clearing and reloading state information as needed, thereby achieving thread isolation through time-division rather than spatial replication. This periodic action dramatically reduces power consumption by keeping state memory dormant when not actively used by a particular thread.
Solution Approach 2:
The patent employs a discard-and-recover strategy for circuit state between thread executions. Instead of maintaining persistent replicated state for multiple threads, the circuit discards state information when switching between threads and recovers necessary state information on-demand. This approach maintains thread isolation while minimizing the energy required for state maintenance.
Data Source
AI summary
A method for designing a system on a target device includes modifying a circuit to enable the circuit to support a plurality of threads at an instant of time. An interface is generated that enables one or more of the plurality of threads to be swapped out of an execution queue for accessing the circuit and that enables one or more other threads to be swapped into the execution queue for accessing the circuit, wherein at least one of the modifying and the generating is performed by a processor.