Temporary Effective Address for Coherent Accelerator Page Fault Resolution
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Solution Overview
Problem
FPGA-based coherent accelerators face challenges in resolving page faults out of context for shared contexts, as they generate asynchronous interrupts that cannot be directly handled by the processor, leading to difficulties in identifying the process causing the fault and resolving it.
Innovation Solution
The system creates a temporary effective address associated with a virtual segment identifier (VSID) in the processor's address space when an asynchronous interrupt occurs, allowing the processor to recreate the page fault and enabling the operating system to resolve it by invoking the page fault handler.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If shared contexts are used to allow multiple processes to access the coherent accelerator, then resource utilization is improved, but page fault resolution becomes complex because the processor cannot directly identify which process caused the fault
Solution Approach 1:
The patent introduces a temporary effective address as an intermediary mechanism. When a page fault occurs in a shared context, the system creates a temporary effective address that maps to the faulting virtual address in the current process's address space. This temporary address acts as a mediator that allows the processor to recreate the page fault in the context of the current process, enabling proper fault resolution without needing to track which process caused the fault.
Solution Approach 2:
The system performs preliminary action by creating the temporary effective address before attempting to resolve the page fault. This temporary address is set up in advance to facilitate the recreation of the page fault in the appropriate process context, ensuring that the fault can be resolved correctly even though the interrupt arrived out of context.
2Adaptability or versatility
If asynchronous interrupts are generated by the coherent accelerator, then processing flexibility is improved, but the processor cannot directly handle the interrupt in the context of the faulting process
Solution Approach 1:
The temporary effective address serves as an intermediary that bridges the gap between the asynchronous interrupt arrival and the faulting process context. By creating this temporary address mapping, the system enables the processor to recreate the page fault in the context of the current process, making the asynchronous interrupt handling as straightforward as synchronous interrupt handling.
3Productivity
If the coherent accelerator allows direct memory access with effective addresses, then data transfer efficiency is improved, but the operating system cannot perform conventional address translation and memory protection
Solution Approach 1:
The temporary effective address acts as an intermediary that restores the operating system's ability to perform memory protection and address translation. When a page fault occurs, the temporary address allows the OS to recreate the fault in the appropriate process context, enabling conventional memory protection mechanisms to function correctly while maintaining the efficiency benefits of coherent acceleration.
Data Source
AI summary
Systems, methods, and computer program products to perform an operation comprising creating, by a kernel, a temporary effective address associated with a virtual segment identifier (VSID), wherein the VSID is received by a processor in an asynchronous interrupt generated by a coherent accelerator in response to a page fault generated by the coherent accelerator in executing an instruction, accessing the temporary effective address by the processor to recreate the page fault on the processor, and resolving the page fault by an operating system executing on the processor.