Temporary Fixing Layer Layout for Low-Step Redistribution Wiring
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Solution Overview
Problem
The formation of a sealing layer for semiconductor chips on temporary fixing materials leads to a step between the chip and the sealing layer, causing stress singularities due to thermal expansion coefficient differences, which can result in cracks or peeling in the redistribution layer, especially when fine wiring and thin insulating layers are involved.
Innovation Solution
A method involving a carrier substrate with a temporary fixing material layer, where a semiconductor chip is arranged and sealed, and a redistribution layer with multilayer wiring and insulating layers is formed, with careful selection of temporary fixing material thickness and support elastic modulus to maintain a step of 5.0 μm or less, reducing stress singularities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a sealing layer is formed over a semiconductor chip on a temporary fixing material layer, then the chip is sealed and protected, but a step is formed between the chip and sealing layer causing stress singularities
Solution Approach 1:
The patent applies preliminary action by forming a recess in the temporary fixing material layer before arranging the semiconductor chip. This pre-prepared recess ensures that when the sealing layer is formed over the chip, the chip surface remains substantially flush with the sealing layer surface, preventing step formation and subsequent stress singularities while maintaining proper sealing integrity.
Solution Approach 2:
The patent changes the geometric parameters of the temporary fixing material layer by creating a recess with specific dimensions. The recess has a bottom surface and side surfaces that accommodate the chip thickness, ensuring the chip top surface aligns with the sealing layer surface. This parameter modification eliminates the step discontinuity that would otherwise cause stress concentration.
2Manufacturing precision
If the semiconductor chip protrudes higher than the sealing layer surface, then the chip can be properly positioned, but a minute step is formed causing stress concentration
Solution Approach 1:
The recess is formed in advance in the temporary fixing material layer to precisely accommodate the semiconductor chip. This preliminary structural preparation ensures that the chip is positioned at the correct height, with its top surface substantially flush with the future sealing layer surface, preventing both excessive protrusion and depression that would compromise redistribution layer integrity.
Solution Approach 2:
The recess in the temporary fixing material layer acts as an intermediary structure that mediates between the chip and the sealing layer. By providing this intermediate recess space, the chip can be properly positioned and supported while ensuring its surface aligns with the sealing layer, thereby preventing stress concentration points that would affect redistribution layer reliability.
3Productivity
If a redistribution layer with fine wiring and thin insulating layer is formed, then wiring density is increased, but stress singularity causes cracks or peeling
Solution Approach 1:
The recess in the temporary fixing material layer is formed before creating the redistribution layer. This preliminary structural preparation ensures a substantially flush surface between the chip and sealing layer, eliminating stress singularities before the fine wiring and thin insulating layers are deposited. This prevents subsequent cracks or peeling in the high-density redistribution layer.
Solution Approach 2:
The recess structure serves as a beforehand cushioning measure by pre-compensating for potential height mismatches between the chip and sealing layer. By accommodating the chip in this pre-formed recess, the structure prevents the formation of stress concentration points that would otherwise cause cracks or peeling in the subsequently formed fine-wired redistribution layer.
Data Source
AI summary
A method for manufacturing a semiconductor device, comprising: arranging a semiconductor chip on a temporary fixing material layer of a carrier substrate; forming a sealing layer sealing the semiconductor chip, thereby forming a sealing structure on the carrier substrate, the sealing structure having a connection surface in contact with the temporary fixing material layer, the semiconductor chip being exposed to the connection surface, a step formed by the semiconductor chip and the sealing layer on the connection surface being 5.0 μm or less; separating the carrier substrate from the sealing structure; and providing a redistribution layer on the connection surface.