10-Transistor Volatile Memory Cells With Dynamic Write Margin Control
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Solution Overview
Problem
Volatile memory elements in integrated circuits, such as those used in programmable logic devices, are susceptible to soft error upsets caused by cosmic rays and radioactive impurities, leading to data corruption and performance issues, particularly in remote telecommunications equipment where maintenance is burdensome.
Innovation Solution
The implementation of robust memory cells with ten transistors, using adjustable power supply voltages and signal magnitudes during write operations, and body biasing to enhance immunity to soft error upsets, ensuring data integrity and successful data loading operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional volatile memory elements are used, then device complexity is reduced, but soft error upset immunity deteriorates
Solution Approach 1:
The memory cell is divided into multiple functional blocks including first and second cross-coupled inverter circuits, first and second latch circuits, and associated transistor networks. This segmentation allows each block to perform specific functions that collectively enhance soft error upset immunity while maintaining manageable complexity through modular design.
Solution Approach 2:
The memory cell structure is designed with redundant latch circuits and cross-coupled inverters that are pre-configured to detect and correct soft error upsets before they propagate. The preliminary action is embedded in the circuit topology itself, which automatically responds to radiation-induced errors through its inherent feedback mechanisms.
2Reliability
If robust memory cell structures are implemented, then soft error upset immunity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs parameter changes in the form of adjustable power supply voltages (VCC1, VCC2) and body biasing voltages (VB1, VB2) to optimize memory cell performance. By dynamically adjusting these electrical parameters, the cell can enhance its soft error upset immunity without requiring fundamental changes to the manufacturing process, thus maintaining ease of fabrication while improving reliability.
Solution Approach 2:
The memory cell structure serves multiple functions simultaneously: data storage, soft error detection, and error correction. The cross-coupled inverter circuits and latch circuits work together to provide both normal memory operation and radiation error immunity, reducing the need for separate error correction circuits and simplifying the overall manufacturing process.
3Reliability
If power supply voltages are varied during write operations, then write margin is enhanced, but energy consumption increases
Solution Approach 1:
The patent implements dynamic voltage adjustment where power supply voltages VCC1 and VCC2 are varied in real-time during write operations to enhance write margin. During reads, the voltages return to normal levels. This dynamic approach ensures that energy is consumed only when needed for error-prone write operations, optimizing the balance between reliability and power consumption.
Solution Approach 2:
The voltage adjustment occurs periodically during write operations rather than continuously. The power supply voltages are elevated only during the brief window when write operations occur, and return to nominal levels during read operations and idle states. This periodic action significantly reduces overall energy consumption while maintaining enhanced write margin when needed.
Data Source
AI summary
Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors. To overcome difficulties in writing data into the memory elements, signal strengths for one or more of the signals provided to the array may be adjusted. There may be two positive power supply voltages that are used in powering each memory element. One of the power supply voltages may be temporarily lowered relative to the other power supply voltage to enhance write margin during data loading operations. Other signal strengths that may be adjusted in this way include other power supply signals, data signal levels, address and clear signal magnitudes, and ground signal strengths. Adjustable power supply circuitry and data read-write control circuitry may be used in making these signal strength adjustments.