Two-Tensile Dielectric Layer CMP Planarization
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Solution Overview
Problem
Conventional interlayer dielectric (ILD) layer fabrication methods result in significant loss during chemical mechanical polishing due to topography loading effects, leading to uneven height and reduced dielectric material effectiveness.
Innovation Solution
A method involving the deposition of two tensile dielectric layers with varying carbon content, where the second layer has a higher carbon content than the first, using plasma-enhanced chemical vapor deposition, and subsequent treatments to optimize the dielectric constant and CMP process, ensuring minimal dielectric loss and even surface planarization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single layer of silicon dioxide is formed on the substrate, then the fabrication process is simple, but significant material loss occurs during CMP due to topography loading effects
Solution Approach 1:
The patent divides the single dielectric layer into two distinct tensile dielectric layers with different carbon contents. The first layer (lower carbon content) provides mechanical support and stress management, while the second layer (higher carbon content) offers superior CMP resistance. This segmentation allows each layer to perform its specialized function, resolving the contradiction between manufacturing simplicity and material loss prevention.
Solution Approach 2:
The patent employs a composite structure consisting of two dielectric layers with different material compositions (varying carbon contents). This composite approach combines the advantages of both materials: the first layer maintains structural integrity while the second layer provides enhanced resistance to CMP removal, thereby reducing overall material loss during the polishing process.
2Ease of operation
If chemical mechanical polishing is conducted to remove contact metal along with the ILD layer, then the contact metal is effectively removed, but a major portion of the ILD is lost due to topography loading effect
Solution Approach 1:
The patent applies local quality by creating a dielectric layer structure with spatially varying properties. The second layer, positioned where CMP contact occurs, has higher carbon content specifically to provide localized resistance against excessive removal. This local modification allows the ILD to withstand CMP forces while still enabling effective contact metal removal in other areas.
Solution Approach 2:
The patent implements beforehand cushioning by pre-positioning the second tensile dielectric layer with higher carbon content at the interface where CMP will occur. This layer acts as a protective cushion that absorbs the mechanical stress and topography loading effects during CMP, preventing excessive removal of the underlying first layer and maintaining overall height uniformity.
3Speed
If the dielectric constant k is reduced to increase speed, then the capacitance decreases and speed increases, but the ILD layer becomes more susceptible to damage during CMP
Solution Approach 1:
The patent utilizes parameter changes by varying the carbon content in different dielectric layers. The second layer has higher carbon content, which simultaneously achieves two objectives: it maintains a low dielectric constant for high-speed signal transmission while also providing enhanced mechanical strength and CMP resistance. This parameter optimization resolves the contradiction between speed enhancement and structural reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces dielectric constant, minimizes material loss during CMP, and maintains the height of the ILD layers, enhancing semiconductor device performance by maintaining the integrity of the ILD structure.
Implementation Method 1
using plasma-enhanced chemical vapor deposition
Data Source
AI summary
A semiconductor device is disclosed. The semiconductor device includes: a substrate; a first tensile dielectric layer on the substrate; a metal gate in the first tensile dielectric layer; a second tensile dielectric layer on the first tensile dielectric layer; and a contact plug in the first tensile dielectric layer and the second tensile dielectric layer. Preferably, the top surface of the contact plug is even with the top surface of the second tensile dielectric layer, and a carbon content of the second tensile dielectric layer is greater than the carbon content of the first tensile dielectric layer.

