Tensile TEOS Oxide ILD for 3D NAND Crack Prevention
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Solution Overview
Problem
The semiconductor industry faces challenges with cracks and defects in 3D semiconductor chips due to physical stress from thermal expansion differences between inter-level dielectric and interconnection levels in vertical NAND structures, affecting device performance.
Innovation Solution
A method for forming a dielectric film stack for inter-level dielectric (ILD) layers in 3D NAND structures, involving the deposition of a first oxide layer using TEOS and oxygen-containing gases, followed by a second oxide layer using silane and oxygen-containing gases, with specific process conditions to achieve tensile stress and thickness, and a thermal anneal treatment in a nitrogen-rich environment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-layer inter-level dielectric is used to simplify the structure, then device complexity is reduced, but thermal stress concentration causes cracking and defects
Solution Approach 1:
The inter-level dielectric is divided into multiple layers: a first dielectric layer with lower thermal expansion coefficient deposited at lower temperature, and a second dielectric layer with higher thermal expansion coefficient deposited at higher temperature. This segmentation distributes thermal stress across layers, preventing stress concentration and cracking while maintaining structural integrity.
Solution Approach 2:
The patent uses composite dielectric materials with different thermal expansion coefficients arranged in specific layers. The first dielectric layer (e.g., SiO2-based) has lower thermal expansion coefficient than the second dielectric layer (e.g., SiON-based), creating a composite structure that manages thermal stress through material property differentiation.
2Stress or pressure
If high thermal expansion coefficient materials are used in the inter-level dielectric, then stress relief is improved, but thermal stress during processing increases causing defects
Solution Approach 1:
The patent controls thermal stress by changing deposition temperature parameters. The first dielectric layer is deposited at a lower temperature (e.g., 300-400°C) to minimize thermal stress during formation, while the second dielectric layer is deposited at a higher temperature (e.g., 400-500°C) to achieve the desired thermal expansion coefficient for stress relief. This temperature parameter differentiation allows precise control of stress characteristics.
Solution Approach 2:
Different regions of the dielectric structure have different thermal expansion coefficients tailored to specific functional requirements. The first dielectric layer near the transistor structure has lower thermal expansion to protect sensitive devices, while the second dielectric layer has higher thermal expansion to provide overall stress relief, creating local quality differentiation.
3Stress or pressure
If low deposition temperature is used for the inter-level dielectric, then thermal stress is reduced, but film density and mechanical strength decrease
Solution Approach 1:
The dielectric structure is segmented into layers with different deposition temperatures. The first dielectric layer deposited at lower temperature maintains adequate density for electrical isolation, while the second dielectric layer deposited at higher temperature provides enhanced mechanical strength and stress management, allowing each layer to be optimized for its specific function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method reduces stress and defects in the dielectric film stack, enhancing thermal stability and preventing cracking, thereby improving the integrity and performance of 3D NAND structures.
Implementation Method 1
forming on exposed surfaces of the gate stack a first oxide layer using a first RF power and a first process gas comprising a TEOS gas and a first oxygen-containing gas
Implementation Method 2
forming over the first oxide layer a second oxide layer using a second RF power and a second process gas comprising a silane gas and a second oxygen-containing gas
Implementation Method 3
subjecting the substrate to a thermal anneal treatment in a nitrogen rich environment at a temperature of about 700° C. to about 850° C.
Data Source
AI summary
Embodiments of the present disclosure generally relate to an improved method for forming a dielectric film stack used for inter-level dielectric (ILD) layers in a 3D NAND structure. In one embodiment, the method comprises providing a substrate having a gate stack deposited thereon, forming on exposed surfaces of the gate stack a first oxide layer using a first RF power and a first process gas comprising a TEOS gas and a first oxygen-containing gas, and forming over the first oxide layer a second oxide layer using a second RF power and a second process gas comprising a silane gas and a second oxygen-containing gas.