Tensor MAC Array Scheduling for Scalable Chip Layout

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Solution Overview

Problem

The exponential growth in the scale of multiply-accumulate arrays in chips used for tensor computations in intelligent driving and intelligent cockpit applications poses significant challenges for design and physical implementation, necessitating improved layout friendliness and scalability.

Innovation Solution

A tensor computation apparatus with a plurality of multiply-accumulate arrays that can be flexibly scheduled and controlled based on operation type and tensor sizes, allowing for efficient computation of tensors of varying types and sizes, reducing the need for multiple dedicated computation circuits and facilitating scalable circuit layout.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If the scale of multiply-accumulate arrays is increased to meet growing computing power demand, then computing capability is improved, but design complexity and physical implementation difficulty increase exponentially

Engineering Contradiction:
Improvecomputing powerVSAvoiddesign complexity
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The patent divides the large-scale multiply-accumulate array into multiple smaller sub-arrays (e.g., 8 sub-arrays instead of one large array). Each sub-array can be independently controlled and configured, reducing the complexity of designing and implementing a single massive array while maintaining the total computing capacity needed for tensor operations.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If dedicated computation circuits are designed for different tensor operation types and sizes, then computation precision is improved, but device complexity and layout flexibility deteriorate

Engineering Contradiction:
Improvecomputation precisionVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent creates a universal multiply-accumulate array architecture that can handle different tensor operation types (convolution, matrix multiplication, etc.) and sizes through configurable parameters. The same physical hardware structure can be dynamically reconfigured via control signals to perform various computations, eliminating the need for dedicated circuits for each operation type while maintaining computation precision.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces dynamic control mechanisms where the multiply-accumulate array's behavior can be changed during operation through control signals. Parameters such as the number of active sub-arrays, data flow patterns, and accumulation modes can be dynamically adjusted to match the specific computation requirements, allowing one circuit to adapt to multiple operation types and sizes.

Inventive Principle:
Principle #15Dynamics

3Ease of manufacture

If the number of multiply-accumulate arrays is reduced to simplify physical implementation, then ease of manufacture is improved, but adaptability to different tensor sizes and operation types deteriorates

Engineering Contradiction:
Improveease of manufactureVSAvoidadaptability
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

By segmenting the compute unit into multiple smaller sub-arrays, the patent enables easier manufacturing of individual sub-arrays while maintaining overall system versatility. These standardized sub-arrays can be systematically arranged and configured to meet different computational requirements, making the manufacturing process more manageable and repeatable.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs dynamic configuration mechanisms that allow a fixed number of physical arrays to adapt to varying computational demands. Through control signals, the system can activate different numbers and combinations of sub-arrays, adjust data flow paths, and modify accumulation behaviors, thereby achieving high adaptability without requiring a large number of physical arrays.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20260023816A1Tensor Computation Apparatus And Method, Chip, Medium, And Device
Publication Date: 2026.01.22 BEIJING HORIZON INFORMATION TECH CO LTD
  • US20260023816A1 patent drawing
  • US20260023816A1 patent drawing
  • US20260023816A1 patent drawing

AI summary

Embodiments of this disclosure disclose a tensor computation apparatus and method, chip, medium, and device. The apparatus includes: a memory, configured to store a first and a second tensor that are to be computed; a controller, configured to read the first and the second tensor, and an operation type; and a computation component, including a plurality of multiply-accumulate arrays. Any one of the multiply-accumulate arrays is configured to determine a multiply-accumulate result of at least one pair of input values, where any pair includes a first and a second input value. The controller is further configured to: determine, based on the first tensor, the second tensor, and the operation type, a target multiply-accumulate array from the plurality of multiply-accumulate arrays, and determine a corresponding target control mode; and control, according to the target control mode, the target multiply-accumulate array to perform corresponding operations, to obtain a tensor computation result.