Tensor Mapping Memory Layout for Multi-Node Arithmetic Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing arithmetic processing devices require software developers to develop different programs for each node, increasing development burden and costs due to the need for tensor division considerations.
Innovation Solution
An arithmetic processing device with a write-out and read-out processing unit that writes and reads data without deeply considering tensor division, allowing a common program to be used across nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different programs are developed for each node considering tensor division, then the arithmetic processing can be executed correctly, but the development burden and verification costs become extremely high
Solution Approach 1:
The patent introduces a buffer memory as an intermediary component between the plurality of nodes and the external memory. This buffer memory handles the complex data arrangement and tensor division operations, allowing each node to execute the same simple program while the intermediary manages the complexity of data distribution and retrieval across different nodes.
2Reliability
If different programs are developed for each node considering tensor division, then the arithmetic processing can be executed correctly, but the development period becomes longer
Solution Approach 1:
The patent enables a single universal program to be executed on all nodes regardless of the input tensor's division requirements. The buffer memory dynamically adapts the data arrangement based on the number of nodes and tensor shape, allowing the same program to function correctly across different configurations without requiring separate development for each node.
3Productivity
If high-resolution image information is input requiring division into multiple pieces, then the processing can be distributed across nodes, but the data arrangement complexity increases
Solution Approach 1:
The buffer memory serves as an intermediary that automatically handles the complex data arrangement when high-resolution image information is divided across multiple nodes. It manages the mapping between input data and node assignments based on the number of nodes and tensor shape, eliminating the need for developers to manually manage this complexity.
Solution Approach 2:
The system enables self-service by allowing the buffer memory to automatically adapt its data arrangement based on the input tensor's characteristics and the number of available nodes. The same program automatically adjusts its behavior to suit different configurations without requiring external intervention or reprogramming.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
It is an object of the present disclosure to provide an arithmetic processing device. An arithmetic processing device (1) configured from a network having a plurality of nodes, each of which includes a plurality of processor elements, includes: a write-out processing unit (12) that writes out data of image information, which is input, divided and transposed for each node, to a predetermined area in a memory device (20);a change processing unit (13) that changes a correspondence relationship between the predetermined area of the memory device and the node in accordance with a tensor shape of the image information; and a read-out processing unit (14) that reads out the data stored in the memory device to a corresponding node.