AI Tensor Network Reduction for Quantum Circuit Gate Pruning

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Quantum computing faces challenges with overparameterization, leading to inefficiencies in quantum circuits due to excessive control gates, which are limited by hardware constraints.

Innovation Solution

Utilizing machine learning to optimize tensor networks, specifically through ANSATZ models, to determine the importance of gates in quantum circuits and reduce unnecessary gates, thereby simplifying the circuit structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If tensor networks are used to represent quantum circuits with many parameters, then the ability to approximate higher order tensors is improved, but the device complexity and hardware compatibility deteriorate due to excessive control gates

Engineering Contradiction:
Improveapproximation accuracyVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts and removes redundant or less important gates from the quantum circuit based on their importance scores. This extraction process reduces the number of parameters and gates in the tensor network while maintaining the essential functionality, thereby resolving the contradiction between approximation accuracy and device complexity

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the parameter representation by introducing importance scores for each gate and using these scores to determine which parameters (gates) to retain or remove. This parameter-based selection allows the system to optimize the balance between maintaining approximation accuracy and reducing circuit complexity for hardware implementation

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If the number of parameters in tensor networks is increased to improve approximation capability, then the representation power is improved, but the ease of manufacture and hardware implementation worsen due to hardware constraints on control gates

Engineering Contradiction:
Improvetensor approximation capabilityVSAvoidhardware implementation ease
Core Design Contradiction:
Measurement precisionVSEase of manufacture

Solution Approach 1:

The patent extracts unnecessary gates from the quantum circuit based on importance scoring, directly reducing the parameter count to match hardware capabilities. This extraction enables the system to achieve good tensor approximation with fewer parameters that are compatible with hardware constraints

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies partial action by retaining only the most important gates (those with highest importance scores) rather than implementing all possible gates. This partial implementation achieves sufficient approximation capability while staying within hardware gate limits

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20250390773A1Ansatz tensor network reduction
Publication Date: 2025.12.25 DELL PROD LP
  • US20250390773A1 patent drawing
  • US20250390773A1 patent drawing
  • US20250390773A1 patent drawing

AI summary

Techniques for using AI to reduce a tensor network are disclosed. A service receives an ANSATZ model that is structured as a DAG. This input DAG includes nodes and edges. The service receives a vector reflective of an optimization problem. The optimization problem identifies parameters related to the ANSATZ model. The service feeds the input DAG and the vector as input to the ML algorithm. The ML algorithm attempts to optimize the parameters by assigning probabilities to the nodes and edges. The probabilities reflect whether corresponding tensors will be included in an output ANSATZ DAG. The service receives an output ANSATZ DAG from the ML algorithm. The service then applies a probability threshold to the output ANSATZ DAG, resulting in removal of nodes and edges from the output ANSATZ DAG.