Tensor Tiling Compilation for Data Mover Circuit Configuration

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Solution Overview

Problem

Current integrated circuits face challenges in efficiently generating low-level configuration data for data mover circuits from high-level tensor tiling decisions, leading to excessive configuration data that exceeds the limited resources of data mover circuits, resulting in significant runtime overhead.

Innovation Solution

A method is developed to generate and legalize buffer descriptor objects from tensor tiling specifications, ensuring they conform to hardware constraints of data mover circuits, thereby minimizing the number of buffer descriptors and optimizing configuration data usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If brute force approaches are used to generate configuration data for data mover circuits, then complete coverage of tensor tiling decisions is achieved, but the quantity of configuration data exceeds the limited resources of data mover circuits

Engineering Contradiction:

Improvecompleteness of configuration dataVSAvoidquantity of configuration data

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The patent segments the tensor tiling specification into discrete tile combination objects that can be independently processed and combined. This segmentation allows the configuration data generation to be broken down into manageable units that fit within the limited resources of data mover circuits, rather than attempting to generate all configuration data at once.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent merges selected tile combination objects from the first list into the second list, combining multiple tiles into cohesive data transfer operations. This merging reduces the total number of buffer descriptors needed while ensuring complete coverage of the tensor tiling specification, resolving the contradiction between completeness and quantity.

Inventive Principle:

Principle #5Merging (Combining)

2Reliability

If brute force approaches are used to generate configuration data, then all tensor tiling decisions are covered, but external controllers are needed introducing significant runtime overhead

Engineering Contradiction:

Improvecompleteness of data transfer coverageVSAvoidruntime overhead

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary actions by pre-processing the tensor tiling specification into tile combination objects and buffer descriptor objects before execution. This compilation phase prepares all necessary configuration data in advance, eliminating the need for external controllers to intervene during runtime and significantly reducing operational overhead.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system implements self-service by automatically generating and legalizing buffer descriptor objects from the tensor tiling specification without requiring external controller intervention. The data mover circuits can autonomously execute the compiled configuration data, reducing runtime overhead while maintaining complete coverage of data transfer operations.

Inventive Principle:

Principle #25Self-service

3Quantity of substance

If the number of buffer descriptors is reduced to fit hardware constraints, then configuration data resources are optimized, but compliance with hardware constraints must be ensured

Engineering Contradiction:

Improvenumber of buffer descriptorsVSAvoidcompliance with hardware constraints

Core Design Contradiction:

Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent implements a dynamic legalization process that adjusts buffer descriptor objects to comply with hardware constraints. The system dynamically modifies the buffer descriptors based on the specific constraints of the data mover circuit, ensuring compliance while maintaining the reduced number of descriptors. This dynamic adjustment resolves the contradiction between quantity reduction and constraint compliance.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS20250005246A1Compiling a tensor tiling specification to multi-dimensional data mover circuit configurations

Publication Date: 2025.01.02 XILINX INC

AI summary

Compiling a tensor specification for multi-dimensional direct memory access circuit configurations includes generating a first list of tile combination objects from a tensor tiling specification. The first list specifies a sequence of tiles specified by the tensor tiling specification in which each tile object represents a single tile of a tensor data structure. A second list of tile combination objects is generated by combining selected ones of the tile combination objects from the first list. Each tile combination object of the second list represents one or more tile objects. The tile combination objects of the second list are converted into buffer descriptor objects that include buffer descriptor parameters. Each of the buffer descriptor objects that is non-compliant with hardware constraints corresponding to a data mover circuit that is configurable using the buffer descriptor objects is legalized. The buffer descriptor objects are output, as legalized.