TEOS Cap Layer Carbon Reduction for Via Etching
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Solution Overview
Problem
The via self-etching stop problem occurs in conventional copper damascene processes, where the via etching fails to open the underlying copper wiring as the critical dimension of the via hole shrinks to 90 nanometers or beyond, especially in isolated via configurations.
Innovation Solution
A partial-via-first dual damascene process is implemented using a TEOS-based silicon oxide cap layer with reduced carbon content, deposited via plasma-enhanced chemical vapor deposition, which reduces the carbon content to less than 1×10^19 atoms/cm^3, allowing for effective etching and exposure of the copper wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional silicon oxide cap layer with standard carbon content is used in the dual damascene process, then the etching process can be performed, but the via etching stops before exposing the copper wiring due to self-etching stop at 90 nanometers or below
Solution Approach 1:
The patent changes the carbon content parameter of the silicon oxide cap layer from conventional levels to less than 1×10^19 atoms/cm³. This parameter modification eliminates the self-etching stop effect that occurs at 90 nanometers and below, allowing the via etching process to successfully expose the copper wiring while maintaining the required via opening dimensions
Solution Approach 2:
The patent applies local quality by creating a silicon oxide cap layer with specifically controlled low carbon content only in the region where etching occurs. This localized modification of carbon content in the cap layer enables selective etching behavior - allowing complete via etching where needed while maintaining protective functions elsewhere in the structure
2Area of moving object
If the via hole critical dimension is reduced to 90 nanometers or below to increase integration density, then more circuits can be packed, but the via etching fails to open the copper wiring due to self-etching stop
Solution Approach 1:
The patent modifies the carbon content parameter of the silicon oxide cap layer to less than 1×10^19 atoms/cm³, which fundamentally changes the etching behavior at small dimensions. This enables via holes of 90 nanometers and below to be etched completely through to expose the copper wiring, maintaining manufacturing precision even at reduced via hole areas
Solution Approach 2:
The patent performs preliminary action by pre-modifying the carbon content of the silicon oxide cap layer before the etching process. This preliminary modification of the cap layer's chemical composition prepares it to allow complete etching at small dimensions, preventing the self-etching stop problem before it occurs during via fabrication
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process effectively eliminates the via self-etching stop problem by ensuring the TEOS-based silicon oxide cap layer with a carbon content gradient allows for proper etching and exposure of the copper wiring, even at smaller via hole dimensions.
Implementation Method 1
A TEOS-based silicon oxide cap layer is then deposited on the dielectric layer. The TEOS-based silicon oxide cap layer has a carbon content lower than 1×1019 atoms/cm3
Data Source
AI summary
A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×1019 atoms/cm3. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.