TEOS Showerhead Edge Flow for CMP Uniformity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In integrated circuits, existing methods struggle to planarize inter-level dielectric layers effectively and achieve the desired compressive stress in silicon dioxide layers, particularly during chemical-mechanical polish processes.
Innovation Solution
A TEOS delivery showerhead is configured to provide a higher average flow rate per unit area at the edge band, which is at least twice that of the central region, resulting in a thicker silicon dioxide layer at the edge of the wafer, compensating for higher material removal rates during CMP planarization and inducing compressive stress between 125 and 225 MPa.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a uniform TEOS flow rate is applied across the showerhead, then the deposition process is simple to control, but the CMP planarization uniformity deteriorates due to higher material removal at wafer edges
Solution Approach 1:
The showerhead is designed with different flow rates in different regions: the edge band region (within 1/4 inch of the wafer periphery) receives a higher TEOS flow rate than the central region. This local differentiation compensates for the higher CMP removal rate at wafer edges, achieving uniform final thickness across the wafer surface.
2Stress or pressure
If the TEOS flow rate is increased at the wafer edge, then the compressive stress in the silicon dioxide layer improves, but the material thickness uniformity worsens
Solution Approach 1:
The system changes the flow rate parameter spatially across the showerhead, creating a gradient where the edge band region receives at least twice the TEOS flow rate of the central region. This parameter variation simultaneously achieves the desired compressive stress (125-225 MPa) and compensates for CMP non-uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures effective planarization and maintains compressive stress in the silicon dioxide layer, enhancing the stability and performance of integrated circuits by compensating for material removal disparities during CMP processes.
Implementation Method 1
flowing tetraethylorthosilicate, also known as TEOS, in a vapor phase through a TEOS delivery showerhead
Data Source
AI summary
A dielectric deposition tool for forming a silicon dioxide layer on a wafer with a TEOS showerhead which delivers a flow rate per unit area from an edge band of the showerhead that is at least twice a flow rate per unit area from a central region of the showerhead. The edge band extends at least one half inch from an outer edge of the showerhead up to one fourth of the diameter of the wafer. A process of forming an integrated circuit by forming a silicon dioxide layer on a wafer containing the integrated circuit using the dielectric deposition tool. The silicon dioxide layer is thicker under the edge band than under the central region. A subsequent CMP operation reduces the thickness difference between the wafer outer annulus and the wafer core by at least half. The silicon dioxide layer has a compressive stress between 125 and 225 MPa.