Main Memory Bus Access for Co-Processors Facing I/O Bottlenecks

The patent applies universality by enabling the main memory bus to serve dual purposes: its traditional function for CPU-memory communication and a new function for interfacing co-processors and I/O devices. This multi-functional use of the high-bandwidth main memory bus eliminates the need for separate I/O buses, thereby increasing data bandwidth for co-processors and I/O devices while maintaining interface simplicity through a unified bus architecture.

The patent merges the I/O bus function into the main memory bus system, allowing co-processors and I/O devices to communicate directly through the high-bandwidth main memory bus. This consolidation eliminates the communication bottleneck created by separate low-bandwidth I/O buses, enabling faster processing performance without time loss due to communication constraints.

The patent applies segmentation by introducing dedicated interface circuitry within the memory controller that segments and manages different types of bus traffic. This interface circuitry handles memory operations and co-processor/I/O device operations separately, allowing the main memory bus to serve multiple functions simultaneously without excessive contention, thereby enhancing I/O performance while controlling memory system complexity.