Main Memory Bus Architecture for I/O Bandwidth Bottlenecks
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Solution Overview
Problem
Current computer systems face communication bottlenecks due to the lower bandwidths supported by traditional I/O buses, which restrict the performance of co-processors and I/O devices that operate at faster speeds, necessitating a method to interface these devices via the main memory system for enhanced I/O capabilities.
Innovation Solution
The system connects co-processors or I/O devices directly to the main memory bus, allowing them to communicate at higher bandwidths, similar to the main memory bus, thereby eliminating bottlenecks and enhancing performance. This is achieved through the use of TeraDIMM architecture, which integrates non-volatile memory into the DDR-3 or DDR-4 memory channel, enabling parallelism, bandwidth, and scalability advantages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If co-processors and I/O devices interface via traditional I/O bus, then device compatibility and ease of connection are maintained, but communication bandwidth is limited causing performance bottlenecks
Solution Approach 1:
The memory bus is designed to serve multiple functions: it continues to connect the CPU to system memory while also providing an interface pathway for co-processors and I/O devices. This multi-functionality allows high-bandwidth communication for I/O devices without requiring a completely separate bus architecture, thereby improving I/O performance while managing interface complexity through resource sharing.
Solution Approach 2:
The patent introduces memory interface circuitry and controllers as intermediary components between the memory bus and I/O devices. These intermediaries translate and manage data flow between the high-speed memory bus and various I/O devices, enabling bandwidth improvement while maintaining compatibility and managing the complexity of direct connections.
2Speed
If co-processors operate at higher speeds, then processing capability is improved, but communication bottlenecks occur due to lower I/O bus bandwidth
Solution Approach 1:
The patent transitions I/O devices from the traditional I/O bus dimension to the memory bus dimension, effectively changing the communication pathway. By moving co-processors and I/O devices to interface through the memory bus, the system leverages the higher bandwidth capacity of the memory bus architecture, reducing communication delays that would otherwise occur at the slower I/O bus speed.
3Productivity
If main memory bus bandwidth is utilized for I/O devices, then I/O capabilities are enhanced, but memory system complexity increases
Solution Approach 1:
The memory interface is segmented into distinct control and data pathways, with separate controllers managing CPU memory access and I/O device communication. This segmentation allows the memory bus to handle multiple types of traffic efficiently, enhancing I/O capabilities while managing system complexity through organized, modular interface architecture.
Data Source
AI summary
A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.