Output Terminal Backup Circuit With Memory Cells for Low-Power Idle
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing integrated circuits face challenges in maintaining the configuration of multiple output terminals in low-power or idle mode without overconsumption, as previous solutions either require additional complex functional blocks or fail to efficiently manage cross currents and leakage currents.
Innovation Solution
A device comprising multiple voltage level shifting units, each with a memory cell powered by the supply voltage and controlled by a storage signal, which memorizes the state of each output terminal and includes blocking means to suppress cross currents, allowing only leakage currents in idle mode, thereby maintaining the configuration until the circuit returns to normal operating mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional functional blocks are added to backup multiple terminal configurations, then the backup capability is improved, but the device complexity increases
Solution Approach 1:
The patent implements a universal backup mechanism where a single functional block structure (voltage level shifter unit with memory cell) can backup multiple terminal configurations through parallel arrangement. Each unit handles one terminal, but the overall system uses identical modular units rather than complex dedicated circuits for each terminal, achieving multi-functionality through replication of a simple universal unit.
Solution Approach 2:
The backup device is segmented into multiple independent voltage level shifter units, each handling a specific terminal. This segmentation allows each unit to be a simple, standardized module rather than one complex system, reducing the complexity of individual components while maintaining the capability to backup multiple terminals simultaneously.
2Use of energy by moving object
If the internal regulated voltage is cut off in idle mode, then the power consumption is reduced, but the terminal configuration is lost
Solution Approach 1:
The memory cell in each voltage level shifter unit performs a preliminary action by storing the terminal configuration state before the regulated voltage is completely cut off in idle mode. This preliminary storage ensures that when voltage is reduced, the configuration information is already captured and preserved, preventing data loss while enabling power savings.
Solution Approach 2:
The memory cell acts as an intermediary between the voltage level shifter circuit and the external terminal. It buffers the configuration state, allowing the regulated voltage to be cut off for power savings while the memory cell maintains the configuration information. The memory cell mediates between the power-saving requirement and the configuration preservation requirement.
3Loss of energy
If blocking means are added to suppress cross currents, then the power consumption in idle mode is reduced, but the device complexity increases
Solution Approach 1:
The blocking means are merged into the existing voltage level shifter unit structure rather than being added as separate external components. The blocking transistors are integrated within the same unit that contains the memory cell and voltage level shifter circuit, combining multiple functions (voltage shifting, memory storage, and current blocking) into a single integrated module, thus reducing overall device complexity.
Solution Approach 2:
The blocking means are applied locally at each voltage level shifter unit rather than globally across the entire circuit. Each unit has its own blocking transistors that suppress cross currents only in its specific region, allowing power savings to be achieved locally without requiring complex global control mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient power management by maintaining the state of multiple output terminals in low-power mode with minimal power consumption, ensuring reliable logic levels when transitioning from idle to normal mode without the need for additional functional blocks, thus simplifying the integrated circuit design.
Implementation Method 1
The voltage level shift circuit comprises an input stage supplied with an internal regulated voltage and a part for transferring a state of an output function, which is supplied with a supply voltage of the integrated circuit
Implementation Method 2
each comprising a memory cell powered by the supply voltage and controlled by a storage signal, for storing the voltage output state
Implementation Method 3
includes blocking means to suppress cross currents, allowing only leakage currents in idle mode
Data Source
Figure 1
Figure 2
Figure 3
AI summary
The device (1) has voltage level shifting units (2, 2', 2'', 2''') with outputs (O) connected to a tristate buffer (4) and gates of P-channel and N-channel metal oxide semiconductor transistors (Ps, Ns) of an output stage (3), respectively. Each shifting unit has a memory cell that is supplied by supply voltage and is controlled by a storage signal (L-en) for storing an output state of a specific function of the shifting unit in an integrated circuit rest mode where regulated voltage of an integrated circuit is interrupted. An independent claim is also included for a method for actuating an external contact pad and output terminals configuration protecting device.