Semiconductor Terminal Bump Layout for Dense Bonding Connectivity
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Solution Overview
Problem
Current semiconductor devices face challenges in improving electrical characteristics, particularly in the arrangement and configuration of bumps on terminals for wire bonding, which affect the performance and efficiency of semiconductor chips.
Innovation Solution
The semiconductor device incorporates a substrate with a device region, a terminal covering the region, and a combination of pseudo-bumps and genuine bumps arranged in specific densities and sizes to enhance electrical connectivity and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If only genuine bumps connected to wires are used on terminals, then electrical connectivity is ensured, but the terminal area utilization and bonding density are insufficient
Solution Approach 1:
The patent introduces pseudo-bumps as copies that mimic the appearance and structure of genuine bumps but are not connected to wires. These pseudo-bumps are formed by the same wire bonding process, creating dummy bump structures that increase bonding density and terminal area utilization without requiring additional wire connections, thus resolving the contradiction between ensuring electrical connectivity and increasing bonding density
Solution Approach 2:
The patent segments the bump population into two distinct categories: genuine bumps that provide electrical connectivity and pseudo-bumps that provide structural fillers. This segmentation allows the terminal to simultaneously maintain reliable electrical connections through genuine bumps while achieving higher bonding density through the addition of pseudo-bumps in the interspace regions
2Reliability
If bump size is increased to improve electrical characteristics, then connectivity quality improves, but the number of bumps that can be arranged on the terminal decreases
Solution Approach 1:
By creating pseudo-bump copies in the interspace regions between genuine bumps, the patent effectively doubles the number of bump structures on the terminal without increasing the size of individual genuine bumps. This maintains connectivity quality while increasing the total quantity of bump structures, resolving the contradiction between connectivity quality and number of bumps
Solution Approach 2:
The patent utilizes the two-dimensional terminal surface more efficiently by placing pseudo-bumps in the interspace regions between genuine bumps. This dimensional optimization allows both large genuine bumps for quality connectivity and additional pseudo-bumps to increase quantity, transforming the space utilization from a single-arrangement constraint to a multi-zone optimization
Data Source
AI summary
A semiconductor device includes: a substrate; a device region provided in the substrate; a terminal covering the device region in a plan view; a plurality of pseudo-bumps densely arranged on the terminal in a state of being opened from a wire; and at least one genuine bump arranged more sparsely than the plurality of the pseudo-bumps on the terminal in a state of being connected to the wire.