Terminal Cell Layout Matching for Reliable Nanosheet ICs
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Solution Overview
Problem
Existing semiconductor integrated circuit devices face challenges with manufacturing variations and reliability due to the layout of terminal cells under transistors, particularly when using standard cells with interconnects beneath transistors, which leads to increased power consumption and reduced yield.
Innovation Solution
The layout of semiconductor integrated circuit devices includes terminal cells with interconnects positioned under transistors, where the terminal cells have matching dimensions and configurations with adjacent standard cells, reducing manufacturing variations and improving reliability by aligning gate and power line structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If terminal cells are placed at the end of cell rows in conventional layouts, then circuit block termination is achieved, but manufacturing variations increase and reliability decreases due to layout irregularities
Solution Approach 1:
The patent applies the copying principle by creating terminal cells that are exact replicas of standard cells in terms of layout pattern, nanosheet configuration, gate interconnect structure, and power line arrangement. This ensures that the layout pattern at the end of cell rows is identical to that in the middle, eliminating manufacturing variations caused by boundary effects and improving both manufacturing precision and device reliability
Solution Approach 2:
The patent applies local quality by making the terminal cells have the same local structural characteristics as standard cells. Specifically, the nanosheets, gate interconnects, and power lines in terminal cells are configured to match the local layout patterns of adjacent standard cells, ensuring consistent manufacturing conditions across the entire circuit block
2Productivity
If standard cells are scaled down to improve integration degree, then transistor density increases, but off current increases and power consumption rises
Solution Approach 1:
The patent applies parameter changes by transitioning from planar transistors to nanosheet FETs with three-dimensional channel structures. This structural parameter change enables better control of off current while maintaining scaled dimensions, thereby reducing power consumption while preserving high integration degree. The nanosheet configuration allows for improved electrostatic control and reduced short-channel effects
3Productivity
If interconnects are placed on the back of substrate under transistors, then further higher integration is achieved, but layout complexity of terminal cells increases
Solution Approach 1:
The patent applies universality by designing terminal cells with the same multi-functional layout structure as standard cells. The terminal cells incorporate interconnects on the back of the substrate under transistors, gate interconnects extending perpendicular to nanosheets, and power lines extending in the first direction, making the layout structure universal across all cell types and eliminating the need for special terminal cell designs
Data Source
AI summary
In a semiconductor integrated circuit device, a terminal cell is placed at an end of a cell row. A cell having a logical function includes: an active region including a first nanosheet extending in the X direction; and a first power line formed on the back side of a transistor and extending in the X direction. The terminal cell includes: an active region including a second nanosheet extending in the X direction; and a second power line extending in the X direction. The second nanosheet is the same in width and position in the Y direction as the first nanosheet, and the second power line is the same in width and position in the Y direction as the first power line.