Terminal Electrode Layout Over Insulating Regions to Prevent Cracks
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Solution Overview
Problem
Existing semiconductor devices face challenges in enhancing the reliability of terminal electrodes due to stress-related cracks during the connection of conducting wires, which can lead to electrical failures and reduced device performance.
Innovation Solution
The semiconductor device incorporates an insulating layer with a multilayer wiring region and insulating regions without wirings, where terminal electrodes are positioned over the insulating layer at a distance from the wiring region, with optional dummy wirings and porous regions to absorb stress and prevent crack propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If terminal electrodes are positioned close to multilayer wiring regions for compact design, then device area is reduced, but stress-induced cracks occur during conducting wire connection reducing reliability
Solution Approach 1:
The insulating layer is divided into multiple distinct regions: multilayer wiring regions containing conductive structures and insulating regions without wirings. This segmentation allows terminal electrodes to be positioned over insulating regions, isolating them from stress-prone wiring areas while maintaining compact overall device layout through strategic placement of these segmented zones.
Solution Approach 2:
Different regions of the insulating layer are assigned different functional qualities: multilayer wiring regions provide electrical connectivity with multiple conductive layers, while insulating regions provide mechanical support and stress isolation for terminal electrodes. This local differentiation of structural qualities enables terminal electrodes to withstand connection stresses without cracking, while preserving compact device dimensions through optimized regional functionality.
2Ease of manufacture
If conducting wires are connected directly to terminal electrodes over wiring regions, then manufacturing process is simplified, but stress cracks form during wire bonding reducing device reliability
Solution Approach 1:
An insulating region acts as an intermediary substrate between the terminal electrode and the multilayer wiring region below. This intermediary layer provides a mechanically stable, stress-free platform for conducting wire attachment, isolating the terminal electrode from stress propagation that would otherwise occur through adjacent wiring structures during wire bonding operations.
Solution Approach 2:
The insulating region is positioned beforehand under the terminal electrode to provide mechanical cushioning and stress absorption during the subsequent conducting wire connection process. This pre-positioned protective structure prevents stress-induced cracks from forming in the terminal electrode during wire bonding, ensuring reliable electrical connections without compromising device integrity.
3Reliability
If insulating regions without wirings are introduced to protect terminal electrodes, then stress resistance and reliability are improved, but device structure becomes more complex
Solution Approach 1:
The insulating layer structure transitions from a uniform two-dimensional plane to a three-dimensionally organized multilayer system with distinct wiring and insulating regions at different horizontal positions. This dimensional reorganization allows terminal electrodes to be positioned over insulating regions in the planar view, creating vertical stacking of functionality that protects against stress-induced cracks while minimizing the overall device footprint through efficient spatial utilization.
Solution Approach 2:
The insulating region is nested within the overall insulating layer structure, with multilayer wiring regions positioned adjacent to or overlapping in vertical projection with insulating regions. This nested arrangement allows terminal electrodes to be supported by insulating regions while maintaining compact device dimensions, as the insulating and wiring regions are integrated in a space-efficient hierarchical configuration rather than occupying separate additive areas.
Data Source
AI summary
A semiconductor device includes: a chip; a circuit element formed in the chip; an insulating layer formed over the chip so as to cover the circuit element; a multilayer wiring region formed in the insulating layer and including a plurality of wirings laminated and arranged in a thickness direction of the insulating layer so as to be electrically connected to the circuit element; at least one insulating region which does not include the wirings in an entire region in the thickness direction of the insulating layer and is formed in a region outside the multilayer wiring region in the insulating layer; and at least one terminal electrode disposed over the insulating layer so as to face the chip with the at least one insulating region interposed between the at least one terminal electrode and the chip.