Terminal Time Advance Validation for Abnormal TA Detection

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Solution Overview

Problem

Existing timing advance (TA) mechanisms in communication systems are prone to delivering incorrect TAs, leading to uplink synchronization issues, high bit error rates, and interference, especially in scenarios involving terminal movement.

Innovation Solution

A processing method for TA that involves the terminal receiving multiple messages from the base station, analyzing the differences and relationships between these messages, and using preconfigured conditions to determine the accuracy of the TA, thereby identifying and correcting abnormal TAs to maintain uplink synchronization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the terminal uses the latest TA indicated by the base station, then the uplink synchronization is maintained, but the bit error rate increases when the TA is abnormal

Engineering Contradiction:
Improveuplink synchronizationVSAvoidbit error rate
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The terminal compares the latest TA with the previous TA and uses feedback from this comparison to determine whether to adopt the latest TA. When the absolute difference exceeds a threshold, the terminal feeds back that the TA is abnormal and retains the previous TA, thereby maintaining reliability while preventing bit error rate increase.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent changes the parameter selection criterion from always using the latest TA to conditionally selecting between latest TA and previous TA based on the absolute difference threshold. This parameter change strategy allows the system to adapt between synchronization accuracy and error rate prevention.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If the terminal always uses the latest TA from the base station, then the TA mechanism is simple, but the uplink transmission bit error rate increases due to abnormal TAs

Engineering Contradiction:
ImproveTA mechanism complexityVSAvoiduplink transmission bit error rate
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The terminal implements a feedback mechanism that compares consecutive TAs and determines abnormality based on threshold evaluation. This feedback loop adds minimal complexity while effectively preventing abnormal TAs from causing bit errors, thus resolving the contradiction between simplicity and precision.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The terminal performs preliminary evaluation of the TA before using it for uplink transmission by comparing it with the previous TA. This preliminary action prevents abnormal TAs from being applied, thereby reducing bit error rates without significantly increasing overall system complexity.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If the terminal compares multiple TAs to identify abnormalities, then the bit error rate decreases, but the processing complexity increases

Engineering Contradiction:
Improvebit error rateVSAvoidTA processing complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies partial action by comparing only the latest TA with the previous TA rather than analyzing the entire TA history. This limited comparison is sufficient to detect abnormalities while keeping processing complexity low, thus resolving the contradiction between precision and complexity.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The TA validation process is segmented into distinct steps: receiving latest TA, comparing with previous TA, evaluating absolute difference against threshold, and deciding whether to use the latest TA. This segmentation makes the complexity manageable and the process systematic.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20260032612A1Processing method for time advance ta and apparatus
Publication Date: 2026.01.29 HONOR DEVICE CO LTD
  • US20260032612A1 patent drawing
  • US20260032612A1 patent drawing
  • US20260032612A1 patent drawing

AI summary

Embodiments of this application provide a processing method for a time advance TA applied to a terminal. The terminal is in a low-speed moving state. Low-speed moving includes moving with moving speed in a first speed range. The terminal The method includes: receiving a first message that is sent by a base station and that indicates a first TA; receiving, after the first message is received, a second message that is sent by the base station and that indicates a second TA; and in response to satisfying a first condition, sending an uplink signal by using the first TA to obtain an uplink transmission bit error rate satisfying a requirement including being less than a bit error rate threshold. Satisfying the first condition indicates that there is a possibility that the second TA is abnormal.