Terminating Resistor Placement for Signal Reflection Reduction in Stacked Semiconductor Devices
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Solution Overview
Problem
Conventional semiconductor devices face challenges in reducing signal reflection waves when multiple semiconductor chips are stacked, as existing terminating resistor configurations are inflexible and often require large circuit sizes, limiting the ability to match resistance values with the characteristic impedance of transmission channels.
Innovation Solution
The semiconductor device incorporates terminating resistors mounted on the chip stack, connected to the transmission channels via bonding wires, allowing for resistance value matching with the characteristic impedance of the channels to reduce signal reflection, and features adjustable wiring lines for flexible resistance adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional terminating resistor configurations are used in stacked semiconductor chips, then signal reflection can be reduced, but the circuit size becomes large and resistance value adjustment is limited
Solution Approach 1:
The patent moves the terminating resistor from the chip interior to the chip stack exterior, utilizing the vertical stacking dimension. Multiple chips are stacked with terminating resistors mounted on the stack, transforming a two-dimensional chip layout problem into a three-dimensional stack configuration, thereby reducing on-chip circuit size while maintaining signal reflection reduction functionality
Solution Approach 2:
The patent introduces bonding wires as intermediary connection elements between the terminating resistors and the transmission channels. This mediator allows the terminating resistors to be positioned externally on the chip stack while still effectively connecting to and terminating the transmission channels, separating the resistor placement from the chip substrate
2Reliability
If conventional terminating resistor configurations are used, then signal reflection can be reduced, but resistance value matching with characteristic impedance is inflexible
Solution Approach 1:
The patent makes the resistance value adjustable by introducing switching elements that can dynamically select between different resistor values. The switching elements are controlled to connect different terminating resistors to the transmission channels, enabling adaptive resistance matching with characteristic impedance based on operating conditions
Solution Approach 2:
The patent changes the resistance parameter by providing multiple terminating resistors with different resistance values and using switching elements to select the appropriate resistor. This allows the resistance value to be adjusted to match the characteristic impedance of the transmission channel, optimizing signal quality for different operating conditions
3Reliability
If on-chip terminating resistors are used, then signal reflection is reduced, but design flexibility is limited
Solution Approach 1:
The patent extracts the terminating resistor from the chip substrate and places it externally on the chip stack. This separation allows independent optimization of the chip design and the terminating resistor configuration, providing greater design flexibility while maintaining the signal reflection reduction function
Data Source
AI summary
A semiconductor device includes: a wiring board including first to third bonding pads; a chip stack including semiconductor chips, each chip having first to third connection pads, the first connection pads being connected in series to each other and to the first bonding pad through first bonding wires to form a first transmission channel, the second connection pads being connected in series to each other and to the second bonding pad through second bonding wires to form a second transmission channel, and the third connection pads being connected in series to each other and to the third bonding pad through third bonding wires to form a third transmission channel; and at least one of a first and a second terminating resistor being provided above the chip stack, the first resistor being connected to the first and second channels, the second resistor being connected to the first and third channels.