Termination Circuit Topology for Pad Capacitance Compensation
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Solution Overview
Problem
High-speed integrated circuitry, such as ADC and DAC, face performance issues with wideband frequency response and step response due to parasitic capacitance at connection pads, making it difficult to achieve the desired -3dB point and ideal step response, especially in wideband applications like DC to 20 GHz.
Innovation Solution
The use of a termination circuit comprising resistors and inductors connected in specific ratios to compensate for parasitic capacitance, with the resistance of the substrate maximized to minimize the impact of parasitic capacitance, and the termination circuit comprising passive or active components that can be variable or fixed, to tune out performance issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a wideband frequency response (DC to 20 GHz) is targeted, then the bandwidth is improved, but parasitic capacitance at connection pads causes the actual -3dB point to drop to 16 GHz and step response to creep up instead of reaching 100%
Solution Approach 1:
The patent converts the harmful parasitic capacitance at connection pads into a beneficial element by introducing compensating parasitic elements (inductors and resistors) that cancel out the unwanted capacitance effects. The termination circuit uses an inductor L in parallel with resistor R2, where the inductor's parasitic series resistance and the resistor values are specifically designed to compensate for the pad capacitance, transforming the harmful effect into improved wideband performance.
Solution Approach 2:
The patent changes the termination circuit parameters from a simple resistor to a complex network involving inductor L and resistors R1 and R2 with specific relationships (R1 = 9R2, Rsub = 9R2). These parameter changes are designed to create a frequency-dependent termination that compensates for parasitic capacitance across the wideband range, improving both the -3dB point and step response accuracy.
2Measurement precision
If digital filtering with many taps is used to compensate for error, then the frequency response accuracy is improved, but the device complexity increases significantly
Solution Approach 1:
The patent extracts the compensation function from the digital domain to the analog domain by implementing a termination circuit with passive components (inductor and resistors) that directly compensate for parasitic capacitance effects. This eliminates or reduces the need for complex digital filtering with many taps, maintaining frequency response accuracy while significantly reducing device complexity.
Solution Approach 2:
The patent introduces a passive termination circuit as an intermediary between the signal source and load that actively compensates for parasitic effects. This intermediary circuit (comprising L, R1, R2) serves as a mediator that corrects frequency response errors before they propagate through the system, replacing the need for complex digital post-processing.
3Object-affected harmful factors
If the substrate resistance is maximized, then the impact of parasitic capacitance is minimized, but the manufacturing process becomes more difficult
Solution Approach 1:
Rather than solely relying on maximizing substrate resistance (which complicates manufacturing), the patent converts the parasitic capacitance problem into a solvable circuit design challenge by introducing compensating passive elements. The termination circuit with specific L, R1, and R2 values compensates for pad capacitance effects without requiring extreme substrate resistance values, thus avoiding manufacturing difficulties while still minimizing parasitic impact.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively improves the frequency response and step response performance of high-speed integrated circuitry by compensating for parasitic capacitance, allowing for wider bandwidth and closer alignment with ideal performance metrics, such as achieving a -3dB point at 20 GHz and near-instant step response to 100%.
Implementation Method 1
The resistors and the inductor are connected (together) so as to compensate for parasitic capacitance at, or associated with, or of, the connection pad
Implementation Method 2
a termination circuit to the signal path, the termination circuit comprising an inductor L and two resistors R1 and R2
Data Source
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AI summary
There is disclosed herein integrated circuitry, comprising a signal path connected to a connection pad, for connection to external circuitry; and a termination circuit connected between the signal path and a voltage reference, wherein the termination circuit comprises a resistor and an inductor. The resistor and the inductor are connected together so as to compensate for parasitic capacitance associated with the connection pad. The signal path may carry an output signal from high-speed circuitry such as digital-to-analogue converter circuitry.