Termination Control Circuit for Dynamic Write-Termination Timing

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Solution Overview

Problem

In electronic devices, high-speed data transmission can lead to impedance mismatch phenomena, which existing termination circuits struggle to effectively address, particularly in semiconductor devices lacking efficient control over termination resistor activation periods during write operations.

Innovation Solution

The implementation of a termination control circuit that generates a termination enablement signal to activate a termination resistor during write operations, with adjustable activation periods based on the presence of a write command, and includes signal generation circuits for termination-on and termination-off signals to optimize the termination operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the termination resistor is activated continuously during write operations, then impedance matching is maintained, but power consumption increases

Engineering Contradiction:
Improveimpedance matchingVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The termination resistor is activated periodically only during the specific period when data is actually transmitted on the data line, rather than continuously. The termination control circuit generates a termination enablement signal that activates the termination resistor during the write operation period when impedance matching is needed, and deactivates it when data transmission is not occurring, thus maintaining impedance matching reliability while reducing power consumption.

Inventive Principle:
Principle #19Periodic action

2Reliability

If the termination resistor activation period is extended, then impedance matching is improved, but power consumption increases

Engineering Contradiction:
Improveimpedance matchingVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The termination control circuit dynamically adjusts the activation period of the termination resistor based on the actual write operation timing. The circuit detects when write operations are performed and activates the termination resistor only during those specific time windows, making the termination period dynamic rather than fixed or continuous, thereby optimizing the balance between impedance matching effectiveness and power consumption.

Inventive Principle:
Principle #15Dynamics

3Use of energy by moving object

If the termination control circuit adjusts activation period based on write commands, then power consumption is reduced, but device complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoidcontrol circuit complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The termination control circuit is integrated into the existing memory device architecture and utilizes the same command detection and control signal generation mechanisms already present for write operations. By leveraging the existing control infrastructure, the circuit achieves multi-functionality - using the same control pathways for both write operation management and termination resistor control - thereby reducing the added complexity while still achieving dynamic power optimization.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11342012B2Electronic devices executing a termination operation
Publication Date: 2022.05.24 SK HYNIX INC
  • US11342012B2 patent drawing
  • US11342012B2 patent drawing
  • US11342012B2 patent drawing

AI summary

An electronic device includes a termination control circuit and a data input/output (I/O) circuit. The termination control circuit is configured to generate a termination enablement signal which is activated during a termination operation period for activating a termination resistor while a write operation is performed. In addition, the termination control circuit is configured to adjust a period that the termination enablement signal is activated according to whether a write command is inputted to the termination control circuit during a set detection period of the write operation. The data I/O circuit is configured to receive data by activating the termination resistor during a period that the termination enablement signal is activated when the write operation is performed.