Termination Structures for Stacked Memory Arrays

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Solution Overview

Problem

The formation of T-intersections in stacked memory arrays during the etching process for electrical isolation of memory cells is challenging, leading to inadequate separation and potential electrical shorts, which can result in reduced memory cell density and stability issues due to semiconductor structure movement.

Innovation Solution

The use of tailored termination structures with tabs or prongs, such as rectangular or tapered profiles, to isolate memory cell blocks without forming T-intersections, allowing for concurrent formation of contacts and termination structures that reduce stress and movement of semiconductor structures during processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If T-intersections are formed during etching for electrical isolation, then memory cell blocks can be separated, but inadequate separation and potential electrical shorts occur

Engineering Contradiction:
Improveelectrical isolationVSAvoidseparation quality
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent divides the isolation structure into multiple segments: the original T-intersection etch pattern is segmented into L-intersections with intermediate dielectric regions, and further segmented into separate etch regions (first and second etch regions) that are isolated by intermediate dielectric material. This segmentation prevents direct electrical connection between adjacent memory cell blocks while maintaining adequate separation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediate dielectric structures (liner layers, mandrels, and dielectric material) as mediators between adjacent memory cell blocks. These intermediate structures physically separate the etch regions and prevent direct T-intersection formation, thereby eliminating electrical shorts while maintaining proper isolation.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If conventional etching processes are used, then processing can be simplified, but semiconductor structure movement occurs leading to reduced stability

Engineering Contradiction:
Improveprocessing simplicityVSAvoidsemiconductor structure stability
Core Design Contradiction:
Ease of manufactureVSStability of the object's composition

Solution Approach 1:

The patent performs preliminary actions by forming liner layers and mandrels before the main etching process. These preliminary structures serve as protective frameworks that constrain semiconductor structures during subsequent etching and processing steps, preventing movement and maintaining stability throughout the manufacturing process.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces protective dielectric layers and liner structures beforehand to cushion and protect semiconductor structures from stress and movement during processing. These cushioning layers absorb mechanical stress and prevent structure displacement, ensuring stability without complicating the overall manufacturing process.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Quantity of substance

If memory cell density is increased, then storage capacity improves, but formation of dummy memory cells increases reducing effective density

Engineering Contradiction:
Improvememory cell densityVSAvoideffective memory cell density
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent segments the memory array into distinct first and second etch regions separated by intermediate dielectric structures. This segmentation eliminates the need for dummy memory cells in transition zones, as each region can be independently optimized for maximum cell density without requiring buffer or isolation cells that would reduce effective density.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11177279B2Formation of termination structures in stacked memory arrays
Publication Date: 2021.11.16 MICRON TECHNOLOGY INC
  • US11177279B2 patent drawing
  • US11177279B2 patent drawing
  • US11177279B2 patent drawing

AI summary

In an example, a method of forming a stacked memory array includes forming a stack of alternating first and second dielectrics, forming a termination structure through the stack, the termination structure comprising a dielectric liner around a conductor, forming a set of contacts concurrently with forming the termination structure, forming a third dielectric over an upper surface of the stack and an upper surface of the termination structure, forming a first opening through the third dielectric and the stack between first and second groups of semiconductor structures so that the first opening exposes an upper surface of the conductor, and removing the conductor from the termination structure to form a second opening lined with the dielectric liner. In some examples, the dielectric liner can include a rectangular or a triangular tab or a pair of prongs that can have a rectangular profile or that can be tapered.