Perimeter Termination Trench Layout for Low-Capacitance Semiconductors
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Solution Overview
Problem
The semiconductor industry faces challenges with larger non-active regions in semiconductor devices, which increase parasitic capacitance and affect device performance, necessitating a solution for reduced parasitic capacitance and improved performance.
Innovation Solution
A semiconductor device design featuring a smaller active region with active trenches and a perimeter termination trench surrounded by thicker insulators, which reduces capacitance and enhances breakdown voltage, allowing for improved switching performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If larger non-active regions are used in semiconductor devices, then device area is increased, but parasitic capacitance increases and performance deteriorates
Solution Approach 1:
The patent converts the harmful effect of large non-active regions by introducing termination structures (trenches filled with conductive material) that actively reduce parasitic capacitance. The termination regions are strategically placed at the periphery of active regions to minimize capacitance between adjacent devices while maintaining acceptable device area, thus converting the harmful capacitance effect into a beneficial reduction through careful structural design
2Reliability
If thicker insulators are used in perimeter termination trench, then breakdown voltage is increased, but device complexity increases
Solution Approach 1:
The patent applies local quality by using thicker insulator layers specifically in the perimeter termination trench regions where high breakdown voltage is critical, while using standard insulator thickness in active trench regions. This localized differentiation of insulator thickness optimizes breakdown voltage protection at device peripheries without unnecessarily increasing complexity across the entire device structure
3Object-generated harmful factors
If smaller active region is used, then parasitic capacitance is reduced, but current flow capability is decreased
Solution Approach 1:
The patent applies segmentation by dividing the device into distinct active regions and termination regions, with active trenches containing current-carrying elements separated from peripheral termination trenches. This segmentation allows the active region to be optimized for current flow while termination regions handle capacitance reduction, enabling the device to achieve low parasitic capacitance without sacrificing current flow capability in the active areas
Data Source
AI summary
In one embodiment, a semiconductor device is formed having a plurality of active trenches formed within an active region of the semiconductor device. A first insulator is formed along at least a portion of sidewalls of each active trench. A perimeter termination trench is formed that surrounds the active region. The perimeter termination trench is formed having a first sidewall that is adjacent the active region and a second sidewall that is opposite the first sidewall. An insulator is formed along the second sidewall that has a thickness is greater than an insulator that is formed along the first sidewall.