Ternary Content Addressable Memory Cell With Charge Storage
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Solution Overview
Problem
Ternary content addressable memories face challenges due to high power consumption and large circuit area requirements, as well as difficulties in distinguishing match signals due to insufficient resistance differences in resistive memory transistors.
Innovation Solution
A ternary content addressable memory cell structure is simplified using two transistors with charge storage structures, connected in parallel and coupled to selection and match lines, reducing power consumption and improving signal clarity by maintaining a high ratio of off to on resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a ternary content addressable memory is constructed based on static random access memory structure, then the memory functionality is achieved, but the circuit area occupied is large and power consumption is high
Solution Approach 1:
The patent merges multiple functions into a single memory cell structure. Two transistors with charge storage structures are combined in parallel between the match line and source line, integrating storage and switching functions into one compact unit, thereby reducing the overall circuit area while maintaining ternary content addressable memory functionality
Solution Approach 2:
The memory cell structure is designed to perform multiple functions: the two transistors with charge storage structures can store different charge states (0, 1, or X) and simultaneously act as switches controlled by selection signals. This multi-functionality allows the compact structure to achieve complex ternary content addressable memory operations without requiring separate dedicated components for each function
2Device complexity
If a resistive memory is used to construct ternary content addressable memory, then the memory structure is simplified, but the resistance difference between on and off states is not large enough, making it difficult to judge the sense result
Solution Approach 1:
The patent replaces the resistive memory mechanism with a transistor-based mechanism featuring charge storage structures. Instead of relying on resistance changes, the system uses charge state differences (0, 1, or X) in the transistors to represent ternary values. This substitution provides distinctly different electrical characteristics for each state, enabling clear discrimination of sense results through voltage level detection rather than resistance measurement
3Reliability
If multiple transistors (16) are used to construct a ternary content addressable memory cell, then the memory functionality is achieved, but the power consumption is relatively high
Solution Approach 1:
The patent extracts and removes unnecessary transistors from the conventional 16-transistor structure. By carefully selecting and retaining only the essential two transistors with charge storage structures that are directly involved in storing and accessing ternary data, the design eliminates redundant components that would contribute to power consumption, achieving significant power reduction while preserving core functionality
Solution Approach 2:
The design discards the conventional complex transistor arrangement and recovers functionality through a simplified two-transistor structure. The charge storage structures in these two transistors recover the ternary data storage capability that would otherwise require many more transistors, thereby reducing dynamic and static power consumption associated with additional switching and storage elements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves high-density memory cell layout, low current consumption, quick response times, and accurate match signal generation, addressing the limitations of existing technologies.
Implementation Method 1
The first transistor and the second transistor both have charge storage structures
Data Source
AI summary
A ternary content addressable memory and a memory cell thereof are provided. The ternary content addressable memory cell includes a first transistor and a second transistor. The first transistor has a gate to receive a selection signal. A first end of the first transistor is coupled to a match line. A second end of the first transistor is coupled to a source line. The second transistor has a gate to receive an inverted selection signal. A first end of the second transistor is coupled to the match line. A second end of the second transistor is coupled to the source line. The first and second transistors have charge storage structures.